Report generated on 07-May-2025 at 03:25:04 by pytest-html v3.2.0
2000 tests ran in 113.20 seconds.
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1990 passed, 0 skipped, 10 failed, 0 errors, 0 expected failures, 0 unexpected passes| Result | Test | TIDL Subgraphs | Complete TIDL Offload | Duration | Links |
|---|---|---|---|---|---|
| No results found. Try to check the filters | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1956] | 1 | True | 4.16 | |
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[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_1956' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_1956', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-25' pid=2871334 parent=2854606 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1a0c60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.200s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4676s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4680s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.3443977237269014 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 539593317 bytes MEM: Free's : 26 free's of 539593317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.3443977237269014 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_896] | 1 | True | 1.43 | |
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[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_896' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_896', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-28' pid=2871480 parent=2854008 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458506e30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Resize_896/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_783] | 1 | True | 1.28 | |
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[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_783' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_783', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-38' pid=2879593 parent=2854284 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486878ab50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Resize_783/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1677] | 1 | True | 0.18 | |
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[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_1677' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_1677', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-36' pid=2880971 parent=2854207 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000abac300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3078s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3080s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.371027394144455 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12970373 bytes MEM: Free's : 26 free's of 12970373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.371027394144455 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1600] | 1 | True | 3.55 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_1600' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_1600', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-37' pid=2885626 parent=2854510 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc30dd70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Resize_1600/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_883] | 1 | True | 0.69 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_883' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_883', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-58' pid=2885678 parent=2854224 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9907d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.171s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2740s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 1.3416286662612433 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89076149 bytes MEM: Free's : 26 free's of 89076149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! ------------------------------Captured stderr call------------------------------ Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 177, in perform_tidl_unit_oneprocess pytest.fail(f" max_nmse of {max_nmse} is higher than threshold {threshold}") File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/_pytest/outcomes.py", line 178, in fail raise Failed(msg=reason, pytrace=pytrace) Failed: max_nmse of 1.3416286662612433 is higher than threshold 0.5 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_653] | 1 | True | 4.70 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_653' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_653', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-56' pid=2891937 parent=2853820 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d56fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Resize_653/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1196] | 1 | True | 3.38 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_1196' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_1196', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-60' pid=2892818 parent=2854249 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a651e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Resize_1196/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_731] | 1 | True | 5.10 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_731' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_731', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-84' pid=2920341 parent=2853974 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a092df0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Resize_731/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-84: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Failed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1676] | 1 | True | 4.71 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 no_subprocess = False, tidl_offload = True, run_infer = True, operator_tests_root_fixture = 'tidl_unit_test_data/operator/' test_name = 'Resize_1676' @pytest.mark.parametrize(("test_name"), operator_tests_to_run) def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str): ''' Pytest for tidl unit operator tests using the edgeai-benchmark framework ''' testdir_parent = operator_tests_root_fixture for i in range(len(operator_tests_to_run)): if operator_tests_to_run[i] == test_name: testdir_parent = operator_tests_parent_dir[i] break > perform_tidl_unit(no_subprocess=no_subprocess, tidl_offload = tidl_offload, run_infer = run_infer, test_name = test_name, test_suite = "operator", testdir_parent = testdir_parent) test_tidl_unit.py:70: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ test_tidl_unit.py:89: in perform_tidl_unit perform_tidl_unit_subprocess(tidl_offload = tidl_offload, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ tidl_offload = True, run_infer = True, test_name = 'Resize_1676', test_suite = 'operator' testdir_parent = 'tidl_unit_test_data/operator/Resize' def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str): ''' Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors) Called by perform_tidl_unit ''' kwargs = {"tidl_offload" : tidl_offload, "run_infer" : run_infer, "test_name" : test_name, "test_suite" : test_suite, "testdir_parent" : testdir_parent} p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs) p.start() # Note: This timeout parameter must be lower than the pytest-timeout parameter # passed to the pytest command (on the command line or in pytest.ini) p.join(timeout=600) if p.is_alive(): p.terminate() # Cleanup leftover files for f in glob.glob("/dev/shm/vashm_buff_*"): os.remove(f) > assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}" E AssertionError: Received nonzero exit code: 1 E assert 1 == 0 E + where 1 = <Process name='Process-96' pid=2920593 parent=2853826 stopped exitcode=1>.exitcode test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d301c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 Invoke : ERROR: Unable to open network file ./work_dirs/modelartifacts/8bits/Resize_1676/artifacts/subgraph_0_tidl_net.bin ------------------------------Captured stderr call------------------------------ Process Process-96: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 167, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_inference(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 78, in run_inference self.start_inference() File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 70, in start_inference self.interpreter = self._create_interpreter(is_import=False) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 120, in _create_interpreter interpreter = onnxruntime.InferenceSession(self.kwargs['model_file'], providers=ep_list, File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 387, in __init__ self._create_inference_session(providers, provider_options, disabled_optimizers) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 439, in _create_inference_session sess.initialize_session(providers, provider_options, disabled_optimizers) onnxruntime.capi.onnxruntime_pybind11_state.Fail: [ONNXRuntimeError] : 1 : FAIL : Create state function failed. Return value:-1 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1148] | 1 | True | 0.25 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926424b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2170s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2173s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.67 Core Time (ms) : 4.63 TIDL Subgraphs Processing Time (ms) : 4.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1544] | 0 | - | 0.45 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x592146792bb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.37 Core Time (ms) : 1.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_836] | 0 | - | 0.23 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69f8d3c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1675] | 0 | - | 0.33 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab6bf00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.45 Core Time (ms) : 2.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1862] | 0 | - | 0.20 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638ad6d60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1976] | 0 | - | 8.42 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d15270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3830.35 Core Time (ms) : 3830.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1286] | 0 | - | 0.18 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac6cca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.58 Core Time (ms) : 0.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_122] | 1 | True | 0.55 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a25660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9452s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012952647395713226 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 91.74 Core Time (ms) : 83.16 TIDL Subgraphs Processing Time (ms) : 83.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89076149 bytes MEM: Free's : 26 free's of 89076149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_915] | 0 | - | 0.55 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10051a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 29.66 Core Time (ms) : 29.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_899] | 0 | - | 12.23 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2083eb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 694.94 Core Time (ms) : 694.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1195] | 0 | - | 0.20 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa3d39f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.97 Core Time (ms) : 0.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_395] | 0 | - | 0.23 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b64fb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.68 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1608] | 0 | - | 0.61 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a395ac70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 33.12 Core Time (ms) : 33.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1229] | 0 | - | 0.27 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fd58c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.52 Core Time (ms) : 16.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1817] | 0 | - | 0.22 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219b78d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.28 Core Time (ms) : 1.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1558] | 1 | True | 0.50 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b183aa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.16907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.16932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.16944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.17265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.17279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.17290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.17307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.17323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17469s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 86.00 Core Time (ms) : 83.94 TIDL Subgraphs Processing Time (ms) : 83.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_654] | 1 | True | 0.29 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868762310 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.81s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2148s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2149s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.68 Core Time (ms) : 12.54 TIDL Subgraphs Processing Time (ms) : 12.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1832] | 0 | - | 0.42 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a035520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.24 Core Time (ms) : 15.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_921] | 0 | - | 0.19 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1fef550 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.43 Core Time (ms) : 12.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_873] | 0 | - | 0.17 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce16a00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1453] | 0 | - | 0.26 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc1fd5a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_841] | 1 | True | 1.77 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2a0150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12813s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013933627009714482 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 508.99 Core Time (ms) : 450.22 TIDL Subgraphs Processing Time (ms) : 449.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 253917013 bytes MEM: Free's : 26 free's of 253917013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1783] | 0 | - | 0.31 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4583fd670 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 40.82 Core Time (ms) : 40.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1548] | 0 | - | 0.56 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f951370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 63.71 Core Time (ms) : 63.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1488] | 0 | - | 0.85 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce198a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 579.37 Core Time (ms) : 579.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_628] | 0 | - | 0.19 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ab7f3f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_386] | 0 | - | 0.33 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1ff2050 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 36.18 Core Time (ms) : 36.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_307] | 0 | - | 0.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638ad9980 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_617] | 0 | - | 0.28 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4c0d30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1052] | 0 | - | 0.29 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321aa3960 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.04 Core Time (ms) : 6.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_981] | 0 | - | 0.21 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69f8dba0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.32 Core Time (ms) : 5.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_198] | 0 | - | 0.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b67e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.64 Core Time (ms) : 0.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1354] | 1 | True | 0.41 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492641b30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.22190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.22985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.22999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23335s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05265966571547102 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.57 Core Time (ms) : 38.35 TIDL Subgraphs Processing Time (ms) : 38.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31820165 bytes MEM: Free's : 26 free's of 31820165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_112] | 0 | - | 0.27 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2e99c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.35 Core Time (ms) : 18.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1021] | 0 | - | 0.87 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812eef030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 47.36 Core Time (ms) : 47.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_3] | 0 | - | 0.24 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486867c790 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.60 Core Time (ms) : 16.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1635] | 0 | - | 0.24 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584e9e60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_878] | 0 | - | 1.03 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac58340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 31.45 Core Time (ms) : 31.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1025] | 0 | - | 0.13 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ab81080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_8] | 0 | - | 0.20 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638adb1f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.78 Core Time (ms) : 0.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_798] | 1 | True | 0.26 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a03a870 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.139s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1822s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1825s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.17 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_983] | 0 | - | 0.22 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b6a6d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.62 Core Time (ms) : 16.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1307] | 0 | - | 0.78 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467952f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.16 Core Time (ms) : 15.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1037] | 0 | - | 0.17 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69f8f3f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.83 Core Time (ms) : 8.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_166] | 1 | True | 0.27 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4c1cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5121s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.86 Core Time (ms) : 22.19 TIDL Subgraphs Processing Time (ms) : 22.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_304] | 1 | True | 0.67 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b187850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012952854351498536 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.86 Core Time (ms) : 47.41 TIDL Subgraphs Processing Time (ms) : 47.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65231749 bytes MEM: Free's : 26 free's of 65231749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1292] | 0 | - | 0.30 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321aa4e90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.16 Core Time (ms) : 12.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_325] | 0 | - | 0.24 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac6bca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.50 Core Time (ms) : 14.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_146] | 1 | True | 0.26 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1ff3d60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1590s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.04 Core Time (ms) : 16.57 TIDL Subgraphs Processing Time (ms) : 16.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1935] | 0 | - | 0.08 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc202250 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_564] | 1 | True | 0.46 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1007b40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.20392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.20421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.20457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.20479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.20522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.20542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.20567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.20588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.20607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.20629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.20657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.20683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.20703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.20729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.20750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.20770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.20793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.20814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.20836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.20856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.20877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.20900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.20918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.20936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.20961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.20981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.21004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.21028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.21049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.21067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.21096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.21115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.21132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.21155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.21173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.21190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.34 Core Time (ms) : 24.52 TIDL Subgraphs Processing Time (ms) : 24.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1204] | 1 | True | 0.55 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a29770 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.24264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.24292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.24323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.24344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.24374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.24395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.24421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.24441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.24460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.24482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.24501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.24526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.24549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.25007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.25037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.25055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.25215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.25236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.25256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.25283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.25306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.25308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.25311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.96 Core Time (ms) : 18.69 TIDL Subgraphs Processing Time (ms) : 18.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_183] | 0 | - | 0.31 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868767a20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.69 Core Time (ms) : 5.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1879] | 0 | - | 0.14 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458401f00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_485] | 1 | True | 0.17 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9541d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.76 Core Time (ms) : 7.96 TIDL Subgraphs Processing Time (ms) : 7.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1355] | 0 | - | 0.07 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc202da0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1191] | 0 | - | 0.25 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a079f80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.40 Core Time (ms) : 14.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_840] | 1 | True | 0.71 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638adc240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4636s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.12433564678644056 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 152.15 Core Time (ms) : 125.92 TIDL Subgraphs Processing Time (ms) : 125.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96616845 bytes MEM: Free's : 26 free's of 96616845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1445] | 0 | - | 0.21 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a395da10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.21 Core Time (ms) : 4.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_532] | 0 | - | 0.16 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b6a600 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1359] | 0 | - | 0.16 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549255ac00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.31 Core Time (ms) : 20.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_194] | 0 | - | 0.19 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a039120 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.90 Core Time (ms) : 0.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_817] | 0 | - | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2f6570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1484] | 0 | - | 0.16 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584ecb00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1932] | 0 | - | 0.15 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f957110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.46 Core Time (ms) : 7.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_366] | 0 | - | 0.29 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4c3df0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 31.09 Core Time (ms) : 31.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_93] | 0 | - | 0.30 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac6c810 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.88 Core Time (ms) : 7.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1625] | 0 | - | 0.23 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1ff6990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.43 Core Time (ms) : 10.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_114] | 0 | - | 0.36 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321aa6130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.89 Core Time (ms) : 4.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_926] | 0 | - | 0.30 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c553e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.73 Core Time (ms) : 3.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1048] | 0 | - | 0.17 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a395f3c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.56 Core Time (ms) : 3.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_875] | 1 | True | 1.91 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492646cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.14359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.14427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.14463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.14488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.14517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.14545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.14568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.14589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.14610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.15011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.15041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.15066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001294638754164432 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 456.24 Core Time (ms) : 423.46 TIDL Subgraphs Processing Time (ms) : 423.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 154950101 bytes MEM: Free's : 26 free's of 154950101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1874] | 0 | - | 0.22 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584edb40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.78 Core Time (ms) : 2.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_538] | 0 | - | 0.45 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868768cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.00 Core Time (ms) : 11.00 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_71] | 0 | - | 0.28 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a03a390 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.90 Core Time (ms) : 5.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_169] | 0 | - | 0.31 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a07b150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.47 Core Time (ms) : 14.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_407] | 0 | - | 0.23 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f958420 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.62 Core Time (ms) : 0.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1670] | 0 | - | 0.27 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2ee580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.75 Core Time (ms) : 19.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_487] | 0 | - | 7.27 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3960450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 149.62 Core Time (ms) : 149.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1594] | 1 | True | 0.20 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f20990 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1860s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1863s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.14 Core Time (ms) : 0.99 TIDL Subgraphs Processing Time (ms) : 0.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_280] | 0 | - | 0.18 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce1b230 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.82 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1254] | 0 | - | 2.14 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1ff7400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1419.06 Core Time (ms) : 1419.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1477] | 0 | - | 0.27 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4c5080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.84 Core Time (ms) : 11.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1669] | 0 | - | 0.19 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584eea00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.34 Core Time (ms) : 13.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1489] | 1 | True | 0.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ab83f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.77 Core Time (ms) : 11.61 TIDL Subgraphs Processing Time (ms) : 11.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1092] | 0 | - | 0.68 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a2c1d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.55 Core Time (ms) : 23.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_936] | 1 | True | 0.63 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c56690 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1430s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1433s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545884 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 46.81 Core Time (ms) : 33.14 TIDL Subgraphs Processing Time (ms) : 33.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89076149 bytes MEM: Free's : 26 free's of 89076149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_608] | 1 | True | 9.86 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fd9dc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.125s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060195041117528025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1420.39 Core Time (ms) : 1220.45 TIDL Subgraphs Processing Time (ms) : 1217.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 778891509 bytes MEM: Free's : 26 free's of 778891509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1580] | 1 | True | 0.62 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f959690 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.141s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.17277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.17335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.17375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.17402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.17439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.17462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.17482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.17508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.17529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.17558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.17585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.17604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.17629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.17658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.17721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.17752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.17776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.17985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.18294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.18324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.18326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.18329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 117.84 Core Time (ms) : 97.40 TIDL Subgraphs Processing Time (ms) : 97.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1248] | 1 | True | 0.80 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a03aea0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5487s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 128.93 Core Time (ms) : 124.43 TIDL Subgraphs Processing Time (ms) : 124.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_410] | 0 | - | 0.52 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b18b8c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 28.37 Core Time (ms) : 28.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_782] | 0 | - | 1.11 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321aa6ee0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 55.51 Core Time (ms) : 55.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1466] | 0 | - | 1.67 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2ef500 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 108.57 Core Time (ms) : 108.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_912] | 0 | - | 0.44 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a07c720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.94 Core Time (ms) : 16.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_681] | 0 | - | 0.12 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd328b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1736] | 0 | - | 0.14 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f23370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1826] | 0 | - | 0.47 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466ac560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 250.25 Core Time (ms) : 250.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1028] | 0 | - | 0.12 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac6fbf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1483] | 1 | True | 0.36 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584ef9a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 57.61 Core Time (ms) : 55.82 TIDL Subgraphs Processing Time (ms) : 55.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_435] | 0 | - | 0.23 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868680760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.53 Core Time (ms) : 0.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_997] | 0 | - | 0.12 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638adebf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.59 Core Time (ms) : 0.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_937] | 0 | - | 0.59 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce1d5f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.90 Core Time (ms) : 16.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_78] | 1 | True | 0.27 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4c50c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6678s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.11 Core Time (ms) : 12.35 TIDL Subgraphs Processing Time (ms) : 12.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_63] | 1 | True | 0.36 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac59cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.148s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.23532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.23611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.24033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.24059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.24111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.24147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.24174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.24209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.24234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.24261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.24300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.24326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.24349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.24387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.24421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.24446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.24477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.24505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.24528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.24571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.24597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.24618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.24646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.24680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.24702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.24741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.24764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.24787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.24821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.24848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.24850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.24853s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.46 Core Time (ms) : 45.64 TIDL Subgraphs Processing Time (ms) : 45.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_556] | 1 | True | 0.49 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba100d780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1753s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 124.49 Core Time (ms) : 120.26 TIDL Subgraphs Processing Time (ms) : 120.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_220] | 0 | - | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ab897c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1824] | 0 | - | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638adf560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_34] | 1 | True | 0.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ab87180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6846s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6849s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.12 Core Time (ms) : 2.04 TIDL Subgraphs Processing Time (ms) : 1.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1243] | 0 | - | 0.77 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486876bfc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 45.99 Core Time (ms) : 45.99 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_831] | 0 | - | 0.68 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4c82b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.34 Core Time (ms) : 8.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_600] | 0 | - | 0.40 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a07ce40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.32 Core Time (ms) : 13.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1687] | 1 | True | 0.28 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584f1b00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.146s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.16001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.22962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.23020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.23045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.23088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.23115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.23141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.23172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.23191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.23210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.23235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.23255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.23275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.23310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.23332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.23355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.23377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.23397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.23422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.23450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.23468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.23490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.23516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.23537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.23556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.23581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.23604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.23623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.23647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.23666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.23693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.23717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.23735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.23752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.23781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.23801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.23830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.23855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.23874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.23896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.23927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.23931s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.23934s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.19 Core Time (ms) : 9.58 TIDL Subgraphs Processing Time (ms) : 9.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1462] | 1 | True | 0.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638ae0320 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7511s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00032368505410654264 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.20 Core Time (ms) : 2.99 TIDL Subgraphs Processing Time (ms) : 2.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15050965 bytes MEM: Free's : 26 free's of 15050965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1984] | 0 | - | 0.31 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x592146796a50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.01 Core Time (ms) : 1.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1791] | 0 | - | 0.12 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b18b560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.50 Core Time (ms) : 1.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1361] | 0 | - | 0.19 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab72af0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.44 Core Time (ms) : 2.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1050] | 1 | True | 0.47 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac73ba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13466s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.98 Core Time (ms) : 44.91 TIDL Subgraphs Processing Time (ms) : 44.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_311] | 0 | - | 0.32 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2a5b70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.94 Core Time (ms) : 9.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1818] | 0 | - | 0.30 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f95b600 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.43 Core Time (ms) : 2.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_379] | 0 | - | 0.32 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c58500 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.38 Core Time (ms) : 9.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_713] | 1 | True | 0.30 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a2cd20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3251s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3254s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.82 Core Time (ms) : 9.14 TIDL Subgraphs Processing Time (ms) : 9.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_59] | 0 | - | 0.19 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b18c5c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.66 Core Time (ms) : 18.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1839] | 0 | - | 0.26 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10101f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.67 Core Time (ms) : 12.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1871] | 0 | - | 0.12 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab73c90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_884] | 0 | - | 0.20 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638ae2710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_927] | 1 | True | 0.46 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce1e1b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.145s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.10323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11468s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.98 Core Time (ms) : 10.60 TIDL Subgraphs Processing Time (ms) : 10.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1853] | 0 | - | 0.12 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584f3c70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.54 Core Time (ms) : 1.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1987] | 1 | True | 1.55 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a03d6d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.156s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328231 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 87.02 Core Time (ms) : 62.72 TIDL Subgraphs Processing Time (ms) : 62.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 154240021 bytes MEM: Free's : 26 free's of 154240021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1876] | 0 | - | 4.32 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467978d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2449.35 Core Time (ms) : 2449.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_345] | 1 | True | 0.50 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b18d330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.167s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 68.04 Core Time (ms) : 63.88 TIDL Subgraphs Processing Time (ms) : 63.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_852] | 0 | - | 9.88 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac5e350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 485.44 Core Time (ms) : 485.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_672] | 0 | - | 0.38 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a07db40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.10 Core Time (ms) : 10.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1267] | 1 | True | 0.33 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f95c740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.184s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.94 Core Time (ms) : 7.03 TIDL Subgraphs Processing Time (ms) : 6.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1236] | 0 | - | 0.33 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2a56d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.21 Core Time (ms) : 14.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1071] | 0 | - | 0.27 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45840bb90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 24.65 Core Time (ms) : 24.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1044] | 0 | - | 0.44 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a2f2a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.88 Core Time (ms) : 9.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1793] | 0 | - | 0.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c591e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.97 Core Time (ms) : 4.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_590] | 0 | - | 10.37 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bcccd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 147.23 Core Time (ms) : 147.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_822] | 1 | True | 0.26 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1011440 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.152s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.11 Core Time (ms) : 10.54 TIDL Subgraphs Processing Time (ms) : 10.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1516] | 0 | - | 9.94 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac75cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 106.71 Core Time (ms) : 106.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1772] | 0 | - | 0.23 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321aa8170 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.40 Core Time (ms) : 3.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1399] | 0 | - | 0.15 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa3e03c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_350] | 0 | - | 0.23 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c59fc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.10 Core Time (ms) : 1.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_604] | 0 | - | 0.19 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486876b940 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.25 Core Time (ms) : 1.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_907] | 0 | - | 0.49 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584f55e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 33.93 Core Time (ms) : 33.93 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_944] | 0 | - | 0.44 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce202e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 34.11 Core Time (ms) : 34.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_613] | 1 | True | 0.29 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1013880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.176s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1804s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1808s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.87 Core Time (ms) : 13.11 TIDL Subgraphs Processing Time (ms) : 12.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_599] | 1 | True | 0.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f874970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.165s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2257s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.65 Core Time (ms) : 1.36 TIDL Subgraphs Processing Time (ms) : 1.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_163] | 0 | - | 0.31 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2a6570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.19 Core Time (ms) : 10.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1942] | 0 | - | 0.50 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a07efb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 33.29 Core Time (ms) : 33.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_837] | 0 | - | 0.45 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4ca590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.56 Core Time (ms) : 8.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_420] | 0 | - | 0.16 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219beff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.56 Core Time (ms) : 0.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_79] | 0 | - | 0.23 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486876c530 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.81 Core Time (ms) : 6.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_513] | 0 | - | 1.23 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b18fa00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.75 Core Time (ms) : 27.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1562] | 1 | True | 0.36 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a30130 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.195s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15965s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.28 Core Time (ms) : 5.37 TIDL Subgraphs Processing Time (ms) : 5.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1518] | 0 | - | 0.48 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c5b040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.34 Core Time (ms) : 11.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1920] | 0 | - | 0.11 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8769b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_645] | 0 | - | 0.91 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1015200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 80.65 Core Time (ms) : 80.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1271] | 0 | - | 0.17 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321aa9f20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.27 Core Time (ms) : 2.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_674] | 0 | - | 0.16 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8775f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.77 Core Time (ms) : 1.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1246] | 1 | True | 1.14 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926477d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.170s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.18380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.18415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.18476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.18500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.18530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.18557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.18578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.18600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.18620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.18641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.18668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.18692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.18711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.18743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.18763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.19009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.19317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.19347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.19368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19432s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19436s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101944831958662 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 158.29 Core Time (ms) : 130.05 TIDL Subgraphs Processing Time (ms) : 129.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 154950101 bytes MEM: Free's : 26 free's of 154950101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1205] | 0 | - | 0.13 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2a71f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.66 Core Time (ms) : 1.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_76] | 0 | - | 0.38 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486876d1d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.85 Core Time (ms) : 16.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1088] | 0 | - | 0.27 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2f02e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.95 Core Time (ms) : 8.95 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1825] | 0 | - | 0.59 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce20ec0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.23 Core Time (ms) : 9.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1209] | 0 | - | 1.17 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584f6350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 46.83 Core Time (ms) : 46.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1321] | 0 | - | 0.12 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219c0e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_267] | 1 | True | 0.19 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2ac4e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.20 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_823] | 0 | - | 0.38 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a31df0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.10 Core Time (ms) : 12.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_711] | 0 | - | 0.13 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f878370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.26 Core Time (ms) : 0.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1602] | 0 | - | 3.76 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4cb5f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 79.82 Core Time (ms) : 79.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_463] | 0 | - | 0.12 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69f96030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.38 Core Time (ms) : 3.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1459] | 1 | True | 0.26 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219c2da0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9803s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.52 Core Time (ms) : 3.36 TIDL Subgraphs Processing Time (ms) : 3.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1202] | 0 | - | 0.16 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f962e00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.75 Core Time (ms) : 0.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_23] | 0 | - | 6.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c5b880 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 75.18 Core Time (ms) : 75.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1781] | 1 | True | 0.21 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a084c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.141s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12838s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12842s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.92 Core Time (ms) : 7.86 TIDL Subgraphs Processing Time (ms) : 7.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1604] | 0 | - | 0.94 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2aa520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.58 Core Time (ms) : 13.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_949] | 0 | - | 0.15 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2f1b10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.09 Core Time (ms) : 1.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_489] | 0 | - | 0.13 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868684510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.24 Core Time (ms) : 0.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_984] | 0 | - | 0.25 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1ff8060 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.29 Core Time (ms) : 10.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_193] | 0 | - | 0.75 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f964140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 426.37 Core Time (ms) : 426.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1096] | 1 | True | 0.24 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219c3dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.175s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3621s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.06 Core Time (ms) : 3.93 TIDL Subgraphs Processing Time (ms) : 3.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1065] | 1 | True | 0.43 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a32a00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.195s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.31 Core Time (ms) : 48.15 TIDL Subgraphs Processing Time (ms) : 48.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1550] | 0 | - | 0.83 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a083840 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 17.29 Core Time (ms) : 17.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_243] | 0 | - | 6.13 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2f2250 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 43.20 Core Time (ms) : 43.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_614] | 0 | - | 0.19 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868685330 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.03 Core Time (ms) : 1.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_117] | 0 | - | 0.23 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1ff8d10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.11 Core Time (ms) : 2.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1295] | 1 | True | 0.38 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce219c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2096s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.29 Core Time (ms) : 20.41 TIDL Subgraphs Processing Time (ms) : 20.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_191] | 1 | True | 0.56 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486876fba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.171s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2321s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012946247845935534 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 60.51 Core Time (ms) : 49.85 TIDL Subgraphs Processing Time (ms) : 49.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76366549 bytes MEM: Free's : 26 free's of 76366549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1523] | 0 | - | 0.12 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab3ae0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1004] | 0 | - | 0.30 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a03eee0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.47 Core Time (ms) : 5.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1989] | 0 | - | 0.11 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba101b450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1991] | 0 | - | 7.85 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab0c90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 138.13 Core Time (ms) : 138.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1019] | 1 | True | 0.32 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1ff9fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5742s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.47 Core Time (ms) : 29.43 TIDL Subgraphs Processing Time (ms) : 29.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1369] | 0 | - | 0.94 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a35f30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.90 Core Time (ms) : 3.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1201] | 0 | - | 2.37 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1017a00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.06 Core Time (ms) : 15.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1563] | 0 | - | 0.24 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1907e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.35 Core Time (ms) : 2.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_963] | 0 | - | 0.26 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce241a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.88 Core Time (ms) : 5.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1615] | 1 | True | 7.97 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a040720 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.15780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.15841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.15908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.15934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.16005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.16036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.16068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.16097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.16122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.16150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.16174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.16198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.16226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.16296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.16321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.16349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.16369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.16537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.16616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.16640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.16673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.16695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.16731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.16755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.16784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.16831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.16857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.16883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.16921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.16958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.16983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.17013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.17037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.17061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.17093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.17126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.17152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.17195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.17325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.17542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.17545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.17550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031034458898834637 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 581.71 Core Time (ms) : 385.08 TIDL Subgraphs Processing Time (ms) : 381.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 778891509 bytes MEM: Free's : 26 free's of 778891509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_474] | 0 | - | 0.23 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549255fcb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.58 Core Time (ms) : 1.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1764] | 0 | - | 0.14 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f964860 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.70 Core Time (ms) : 0.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_499] | 0 | - | 0.12 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f13140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_448] | 0 | - | 0.07 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b0a74c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_288] | 0 | - | 0.89 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584f6ff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.12 Core Time (ms) : 11.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1655] | 0 | - | 1.94 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2ac880 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 495.44 Core Time (ms) : 495.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_95] | 0 | - | 0.15 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486877cb60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_991] | 0 | - | 1.24 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce25610 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.51 Core Time (ms) : 8.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1357] | 1 | True | 0.74 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1920e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4897s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4902s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 74.80 Core Time (ms) : 66.51 TIDL Subgraphs Processing Time (ms) : 66.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_181] | 0 | - | 0.08 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d20016f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1683] | 0 | - | 0.44 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69f9a370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.22 Core Time (ms) : 19.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1803] | 0 | - | 0.52 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f87c300 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.14 Core Time (ms) : 10.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_145] | 0 | - | 5.27 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549264aa20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.80 Core Time (ms) : 27.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1778] | 0 | - | 1.25 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1ffea20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.76 Core Time (ms) : 4.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_528] | 0 | - | 0.43 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486868c8f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_774] | 0 | - | 0.60 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a084c80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.48 Core Time (ms) : 3.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1023] | 0 | - | 0.20 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f87dd10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.29 Core Time (ms) : 1.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1304] | 1 | True | 0.41 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868773880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642537 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.62 Core Time (ms) : 8.77 TIDL Subgraphs Processing Time (ms) : 8.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 34884061 bytes MEM: Free's : 26 free's of 34884061 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1640] | 0 | - | 0.30 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a35820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.59 Core Time (ms) : 1.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_953] | 0 | - | 1.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1943f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.46 Core Time (ms) : 6.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_143] | 0 | - | 0.63 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f967370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.03 Core Time (ms) : 3.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1590] | 0 | - | 0.07 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584fdf70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_998] | 0 | - | 0.77 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a37ac0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.15 Core Time (ms) : 5.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1939] | 0 | - | 0.08 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585034d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_723] | 0 | - | 0.44 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868775580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.64 Core Time (ms) : 18.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1418] | 0 | - | 1.87 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584f9e00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.59 Core Time (ms) : 21.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_625] | 0 | - | 1.63 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a085c30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.71 Core Time (ms) : 8.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_434] | 0 | - | 0.40 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce26650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.28 Core Time (ms) : 2.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1946] | 0 | - | 0.13 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1fffa00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.62 Core Time (ms) : 4.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_593] | 0 | - | 0.23 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f968ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.80 Core Time (ms) : 1.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_911] | 1 | True | 6.61 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868776c90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14259s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14266s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060195041117528025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1008.78 Core Time (ms) : 912.61 TIDL Subgraphs Processing Time (ms) : 903.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 778891509 bytes MEM: Free's : 26 free's of 778891509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_477] | 0 | - | 0.60 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d20000c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.53 Core Time (ms) : 7.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_265] | 1 | True | 0.34 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9692e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.244s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3344s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.19 Core Time (ms) : 22.83 TIDL Subgraphs Processing Time (ms) : 22.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_40] | 0 | - | 0.81 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce26b70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.94 Core Time (ms) : 10.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1944] | 0 | - | 0.81 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a37af0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.67 Core Time (ms) : 19.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1059] | 0 | - | 0.06 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b0b50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1881] | 0 | - | 0.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2ad920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.37 Core Time (ms) : 2.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1063] | 0 | - | 0.20 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f96bbf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.18 Core Time (ms) : 2.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_24] | 0 | - | 0.10 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f2e080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_697] | 0 | - | 0.17 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1952f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.62 Core Time (ms) : 3.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_469] | 0 | - | 0.22 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d20007f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.67 Core Time (ms) : 1.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1475] | 0 | - | 0.13 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10189b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.74 Core Time (ms) : 0.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1588] | 0 | - | 0.98 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f96bc80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.98 Core Time (ms) : 19.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1146] | 0 | - | 0.14 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x592146798dc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.82 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_571] | 0 | - | 0.56 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2adf50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.39 Core Time (ms) : 6.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_126] | 0 | - | 0.75 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1019330 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 30.60 Core Time (ms) : 30.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1086] | 0 | - | 1.30 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b196510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 29.07 Core Time (ms) : 29.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1100] | 0 | - | 0.47 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d20015e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.31 Core Time (ms) : 11.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_468] | 0 | - | 0.31 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x592146799980 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.69 Core Time (ms) : 1.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1049] | 1 | True | 0.35 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce27880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.218s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5131s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.60 Core Time (ms) : 24.52 TIDL Subgraphs Processing Time (ms) : 24.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_213] | 1 | True | 1.52 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a38080 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2160s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2165s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001294638754164432 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 222.04 Core Time (ms) : 181.40 TIDL Subgraphs Processing Time (ms) : 181.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 154950101 bytes MEM: Free's : 26 free's of 154950101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1812] | 0 | - | 1.22 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4cc520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 35.25 Core Time (ms) : 35.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1855] | 1 | True | 0.15 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466b0ef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.146s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5260s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.51 Core Time (ms) : 4.32 TIDL Subgraphs Processing Time (ms) : 4.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1234] | 1 | True | 0.26 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a086150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.179s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2618s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.18 Core Time (ms) : 8.07 TIDL Subgraphs Processing Time (ms) : 7.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_743] | 1 | True | 0.82 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2002790 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2060s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 70.36 Core Time (ms) : 59.99 TIDL Subgraphs Processing Time (ms) : 59.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1787] | 0 | - | 0.11 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1c6200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.63 Core Time (ms) : 0.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_312] | 1 | True | 0.80 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce2a300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.186s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3740s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3743s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.48 Core Time (ms) : 27.38 TIDL Subgraphs Processing Time (ms) : 27.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1741] | 1 | True | 1.13 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466b3330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.209s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7457s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7463s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00030957406777050076 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.61 Core Time (ms) : 31.01 TIDL Subgraphs Processing Time (ms) : 30.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96616845 bytes MEM: Free's : 26 free's of 96616845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_88] | 1 | True | 0.17 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458504e20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.143s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1912s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.32 Core Time (ms) : 5.24 TIDL Subgraphs Processing Time (ms) : 5.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12478853 bytes MEM: Free's : 26 free's of 12478853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1494] | 0 | - | 1.72 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b0400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.71 Core Time (ms) : 7.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_684] | 0 | - | 0.97 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a089450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.13 Core Time (ms) : 23.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_127] | 0 | - | 0.12 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f31570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1356] | 0 | - | 0.57 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584fd870 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.30 Core Time (ms) : 4.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_906] | 1 | True | 0.58 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba101aae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6226s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 40.32 Core Time (ms) : 34.00 TIDL Subgraphs Processing Time (ms) : 33.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1455] | 0 | - | 2.95 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f96d280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 85.31 Core Time (ms) : 85.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1302] | 0 | - | 1.90 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b197650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 90.01 Core Time (ms) : 90.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_403] | 0 | - | 0.33 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584fdd70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.40 Core Time (ms) : 6.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_552] | 0 | - | 0.14 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2009610 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1686] | 1 | True | 1.13 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce2c010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8584s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8596s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642532 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 91.83 Core Time (ms) : 73.43 TIDL Subgraphs Processing Time (ms) : 73.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 100503989 bytes MEM: Free's : 26 free's of 100503989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1827] | 0 | - | 0.29 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba101fef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.51 Core Time (ms) : 14.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1837] | 0 | - | 0.32 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f1bd80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 44.49 Core Time (ms) : 44.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_447] | 0 | - | 0.59 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4cd9c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.96 Core Time (ms) : 14.96 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_87] | 0 | - | 0.63 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a089f50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 28.91 Core Time (ms) : 28.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1235] | 0 | - | 3.01 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584fe430 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 30.36 Core Time (ms) : 30.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1047] | 1 | True | 0.83 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59214679ef90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.186s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 70.62 Core Time (ms) : 57.49 TIDL Subgraphs Processing Time (ms) : 57.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1574] | 0 | - | 0.30 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a3a9f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.30 Core Time (ms) : 6.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1738] | 0 | - | 0.29 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba101e670 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.69 Core Time (ms) : 10.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_819] | 1 | True | 0.42 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2006740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.142s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.69 Core Time (ms) : 13.72 TIDL Subgraphs Processing Time (ms) : 13.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1603] | 1 | True | 0.35 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39617a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.202s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6293s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6298s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.05 Core Time (ms) : 12.63 TIDL Subgraphs Processing Time (ms) : 12.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1175] | 0 | - | 1.53 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d182c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.34 Core Time (ms) : 27.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_682] | 0 | - | 0.29 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a3c1e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.36 Core Time (ms) : 9.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_89] | 0 | - | 2.98 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba101f590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 55.89 Core Time (ms) : 55.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_17] | 0 | - | 1.25 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4cd960 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 17.34 Core Time (ms) : 17.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_424] | 0 | - | 0.18 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3963cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.67 Core Time (ms) : 0.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_314] | 0 | - | 0.63 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2009320 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.32 Core Time (ms) : 13.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_324] | 0 | - | 0.25 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a08a530 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.58 Core Time (ms) : 2.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_879] | 0 | - | 0.18 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529951f10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_690] | 0 | - | 0.17 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1c8af0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 34.12 Core Time (ms) : 34.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_641] | 1 | True | 0.67 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39646d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.141s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2249s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2254s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 60.10 Core Time (ms) : 52.42 TIDL Subgraphs Processing Time (ms) : 52.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_958] | 0 | - | 0.53 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce2e890 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.43 Core Time (ms) : 12.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1977] | 0 | - | 0.37 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a3e110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.53 Core Time (ms) : 7.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1416] | 0 | - | 0.16 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466b73f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_72] | 0 | - | 0.35 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b1570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.72 Core Time (ms) : 6.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_580] | 1 | True | 1.07 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a08c290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9011s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013895527128498309 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 152.95 Core Time (ms) : 111.89 TIDL Subgraphs Processing Time (ms) : 110.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 100503989 bytes MEM: Free's : 26 free's of 100503989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1970] | 0 | - | 0.57 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466b8fe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.62 Core Time (ms) : 13.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1036] | 0 | - | 0.16 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5675299551b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.63 Core Time (ms) : 4.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1273] | 0 | - | 0.23 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b3400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.25 Core Time (ms) : 2.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1866] | 0 | - | 3.09 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2009dc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 95.40 Core Time (ms) : 95.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1799] | 0 | - | 0.14 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b752a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_6] | 0 | - | 2.50 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549264af20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 61.53 Core Time (ms) : 61.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1622] | 0 | - | 0.12 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd47ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1126] | 0 | - | 0.32 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2f2f10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.88 Core Time (ms) : 0.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_577] | 0 | - | 0.33 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c5d500 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.82 Core Time (ms) : 8.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_53] | 0 | - | 0.21 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a3e160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.10 Core Time (ms) : 1.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_982] | 0 | - | 0.20 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a397d170 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.07 Core Time (ms) : 1.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_110] | 0 | - | 1.64 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b3670 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.10 Core Time (ms) : 27.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1075] | 0 | - | 0.28 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce30270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.10 Core Time (ms) : 2.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1029] | 0 | - | 0.21 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b0ae2c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_274] | 0 | - | 0.32 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a403c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.51 Core Time (ms) : 4.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1761] | 0 | - | 1.49 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467a3790 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 62.28 Core Time (ms) : 62.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_260] | 0 | - | 0.38 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39687f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.67 Core Time (ms) : 2.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_242] | 0 | - | 0.29 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc20aea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.45 Core Time (ms) : 1.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_516] | 1 | True | 0.30 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4ce6b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.201s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3438s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.05 Core Time (ms) : 9.09 TIDL Subgraphs Processing Time (ms) : 8.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1471] | 0 | - | 0.91 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c5e0f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 24.57 Core Time (ms) : 24.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1583] | 0 | - | 0.63 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b198810 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.34 Core Time (ms) : 4.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_154] | 0 | - | 0.94 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce30fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 44.55 Core Time (ms) : 44.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_705] | 0 | - | 0.22 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d1a5e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.66 Core Time (ms) : 0.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_158] | 0 | - | 0.57 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a43010 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 306.34 Core Time (ms) : 306.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_190] | 0 | - | 1.59 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a08d840 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 31.85 Core Time (ms) : 31.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1481] | 0 | - | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc20be80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.81 Core Time (ms) : 0.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1474] | 0 | - | 0.41 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4d0a90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.74 Core Time (ms) : 7.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1611] | 0 | - | 0.16 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3967f40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.75 Core Time (ms) : 2.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1899] | 0 | - | 0.36 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d1afa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.43 Core Time (ms) : 2.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1997] | 0 | - | 1.03 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f96e1f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 29.48 Core Time (ms) : 29.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_458] | 0 | - | 0.18 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39718f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_97] | 0 | - | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc20cab0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.35 Core Time (ms) : 1.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1860] | 0 | - | 1.63 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b199ff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 70.56 Core Time (ms) : 70.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1183] | 0 | - | 0.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a396a550 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.85 Core Time (ms) : 0.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1224] | 0 | - | 0.21 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa3e7e20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1637] | 0 | - | 0.78 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2f65f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 32.23 Core Time (ms) : 32.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_478] | 1 | True | 0.32 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d1c1c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.199s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2120s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.11 Core Time (ms) : 14.56 TIDL Subgraphs Processing Time (ms) : 14.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1940] | 0 | - | 0.67 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a42840 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 284.75 Core Time (ms) : 284.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1740] | 1 | True | 0.25 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3880b50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10492s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.30 Core Time (ms) : 0.97 TIDL Subgraphs Processing Time (ms) : 0.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_520] | 0 | - | 0.90 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c5fe60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.08 Core Time (ms) : 19.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_557] | 0 | - | 0.19 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa3e95d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_291] | 1 | True | 0.36 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce31c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7100s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7109s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.04 Core Time (ms) : 18.10 TIDL Subgraphs Processing Time (ms) : 17.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1451] | 0 | - | 1.31 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d1ef80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.40 Core Time (ms) : 10.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1513] | 1 | True | 0.56 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4d3f60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6768s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6782s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 65.31 Core Time (ms) : 57.55 TIDL Subgraphs Processing Time (ms) : 57.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_877] | 0 | - | 0.47 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a396d3f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.16 Core Time (ms) : 12.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1805] | 0 | - | 1.30 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fdc740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.98 Core Time (ms) : 9.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_415] | 1 | True | 1.73 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584ff5c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.218s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.09836401365955796 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 519.12 Core Time (ms) : 426.40 TIDL Subgraphs Processing Time (ms) : 425.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 253917013 bytes MEM: Free's : 26 free's of 253917013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1358] | 1 | True | 0.49 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce343d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.230s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.92 Core Time (ms) : 19.10 TIDL Subgraphs Processing Time (ms) : 18.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31820165 bytes MEM: Free's : 26 free's of 31820165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_103] | 0 | - | 2.67 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467a3620 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 155.80 Core Time (ms) : 155.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_254] | 0 | - | 0.21 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1ca6f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.54 Core Time (ms) : 0.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_353] | 1 | True | 0.21 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529958a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.192s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.14573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15029s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15032s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.10 Core Time (ms) : 0.95 TIDL Subgraphs Processing Time (ms) : 0.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_286] | 0 | - | 0.16 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8852e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1419] | 1 | True | 1.57 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2f7620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328231 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 107.30 Core Time (ms) : 72.13 TIDL Subgraphs Processing Time (ms) : 71.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 154240021 bytes MEM: Free's : 26 free's of 154240021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_848] | 0 | - | 1.40 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10201c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 55.64 Core Time (ms) : 55.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1250] | 0 | - | 0.45 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b52f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.67 Core Time (ms) : 2.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_363] | 0 | - | 0.50 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a396d390 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.98 Core Time (ms) : 2.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_951] | 0 | - | 0.89 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f96e760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 47.21 Core Time (ms) : 47.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1708] | 0 | - | 0.18 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab17d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.69 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_670] | 1 | True | 0.57 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56752995b500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.167s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12838s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513113e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.79 Core Time (ms) : 13.46 TIDL Subgraphs Processing Time (ms) : 13.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50492469 bytes MEM: Free's : 26 free's of 50492469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1904] | 0 | - | 0.41 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4d5820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.36 Core Time (ms) : 7.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1155] | 1 | True | 0.39 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c5f980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2634s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.90 Core Time (ms) : 28.64 TIDL Subgraphs Processing Time (ms) : 28.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1440] | 0 | - | 0.60 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a08e4f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 52.24 Core Time (ms) : 52.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1001] | 0 | - | 0.24 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd4d2a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_43] | 0 | - | 0.30 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab2a10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.57 Core Time (ms) : 2.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_392] | 0 | - | 0.14 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f58d10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1299] | 0 | - | 0.18 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b6650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.55 Core Time (ms) : 8.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1390] | 1 | True | 0.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce3b0e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.142s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6648s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.97 Core Time (ms) : 5.93 TIDL Subgraphs Processing Time (ms) : 5.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_94] | 0 | - | 2.84 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac5ecc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 68.48 Core Time (ms) : 68.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_707] | 1 | True | 0.41 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492562540 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0029605766221378117 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.83 Core Time (ms) : 48.57 TIDL Subgraphs Processing Time (ms) : 48.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50492469 bytes MEM: Free's : 26 free's of 50492469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_287] | 0 | - | 0.25 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4d68b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.70 Core Time (ms) : 0.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_252] | 1 | True | 0.25 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3884390 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.183s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3736s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.35 Core Time (ms) : 0.96 TIDL Subgraphs Processing Time (ms) : 0.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_233] | 0 | - | 0.23 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a042d90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.11 Core Time (ms) : 1.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_565] | 0 | - | 0.17 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321abdcc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1374] | 0 | - | 0.14 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c61760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.54 Core Time (ms) : 0.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_109] | 0 | - | 0.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b6730 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.72 Core Time (ms) : 12.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_279] | 0 | - | 0.29 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b19a5b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.45 Core Time (ms) : 2.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1329] | 0 | - | 0.12 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56752995c7e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_918] | 0 | - | 0.37 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868779350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.31 Core Time (ms) : 1.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_49] | 0 | - | 0.16 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd4e910 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_39] | 1 | True | 0.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac7ade0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1752s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.65 Core Time (ms) : 1.60 TIDL Subgraphs Processing Time (ms) : 1.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1495] | 0 | - | 49.45 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab46d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2263.62 Core Time (ms) : 2263.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1109] | 0 | - | 0.56 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c631b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.33 Core Time (ms) : 3.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1581] | 0 | - | 0.43 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f5a040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.42 Core Time (ms) : 16.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_935] | 1 | True | 0.21 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa3edbc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1411s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1414s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.25 Core Time (ms) : 1.17 TIDL Subgraphs Processing Time (ms) : 1.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_11] | 0 | - | 0.22 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d1f0b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.77 Core Time (ms) : 0.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1116] | 0 | - | 0.25 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2086930 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 51.70 Core Time (ms) : 51.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1823] | 1 | True | 0.27 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3887510 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.140s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1735s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.12 Core Time (ms) : 8.96 TIDL Subgraphs Processing Time (ms) : 8.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_397] | 0 | - | 0.20 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56752995d640 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.52 Core Time (ms) : 0.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_111] | 0 | - | 0.56 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a08f7d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 35.55 Core Time (ms) : 35.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_130] | 1 | True | 0.35 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd4f540 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.75 Core Time (ms) : 17.52 TIDL Subgraphs Processing Time (ms) : 17.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_796] | 1 | True | 0.46 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fdd080 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.156s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.31 Core Time (ms) : 19.65 TIDL Subgraphs Processing Time (ms) : 19.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1130] | 1 | True | 0.30 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f885c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.92 Core Time (ms) : 6.78 TIDL Subgraphs Processing Time (ms) : 6.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_22] | 0 | - | 0.18 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b7520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1659] | 1 | True | 0.23 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492564720 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.07 Core Time (ms) : 4.00 TIDL Subgraphs Processing Time (ms) : 3.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_692] | 0 | - | 0.17 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ab917e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_647] | 0 | - | 0.31 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b19b0b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.05 Core Time (ms) : 1.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_961] | 0 | - | 0.15 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f20540 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.60 Core Time (ms) : 0.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_323] | 0 | - | 0.93 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a47510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 44.13 Core Time (ms) : 44.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_142] | 0 | - | 0.31 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4d9340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.83 Core Time (ms) : 19.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_758] | 1 | True | 0.26 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d1fcf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.49 Core Time (ms) : 13.72 TIDL Subgraphs Processing Time (ms) : 13.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1177] | 1 | True | 0.31 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1f9f7e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.206s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.79 Core Time (ms) : 9.49 TIDL Subgraphs Processing Time (ms) : 9.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1222] | 0 | - | 0.14 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bcfa20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_272] | 0 | - | 0.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3972dd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.48 Core Time (ms) : 9.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1652] | 0 | - | 0.31 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486877ab40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.09 Core Time (ms) : 2.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_480] | 0 | - | 0.25 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b7c80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.26 Core Time (ms) : 14.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_724] | 1 | True | 0.69 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac79e70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1404s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.60 Core Time (ms) : 28.61 TIDL Subgraphs Processing Time (ms) : 28.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1381] | 0 | - | 0.17 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f21330 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.33 Core Time (ms) : 4.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_340] | 0 | - | 0.57 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492650f60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.32 Core Time (ms) : 15.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_781] | 1 | True | 0.17 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bd2710 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1602s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1605s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.84 Core Time (ms) : 3.81 TIDL Subgraphs Processing Time (ms) : 3.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1314] | 0 | - | 0.17 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0447c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.94 Core Time (ms) : 0.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1107] | 0 | - | 0.15 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd51bb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_760] | 0 | - | 0.33 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f971680 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.39 Core Time (ms) : 7.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_895] | 0 | - | 0.47 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b19c0f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.44 Core Time (ms) : 2.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_863] | 1 | True | 0.86 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d22150 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2002s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2004s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545884 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 84.82 Core Time (ms) : 73.15 TIDL Subgraphs Processing Time (ms) : 73.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89076149 bytes MEM: Free's : 26 free's of 89076149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_384] | 0 | - | 0.77 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d200c6a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 66.09 Core Time (ms) : 66.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_172] | 0 | - | 1.22 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4d9b30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 82.17 Core Time (ms) : 82.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1400] | 0 | - | 0.49 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3973380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.33 Core Time (ms) : 22.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_446] | 1 | True | 0.31 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b7a000 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2015s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2017s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.55 Core Time (ms) : 4.44 TIDL Subgraphs Processing Time (ms) : 4.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_850] | 0 | - | 0.16 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2092410 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1018] | 0 | - | 1.48 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fdf2e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 48.86 Core Time (ms) : 48.86 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_380] | 0 | - | 0.51 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bd0650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.69 Core Time (ms) : 11.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1511] | 0 | - | 0.36 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1cf020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.75 Core Time (ms) : 12.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_189] | 0 | - | 0.50 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce3b7b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 260.53 Core Time (ms) : 260.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_341] | 0 | - | 0.41 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a08f950 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.03 Core Time (ms) : 16.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_703] | 0 | - | 0.33 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0458e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.33 Core Time (ms) : 10.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_56] | 0 | - | 0.32 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1020b70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.90 Core Time (ms) : 20.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1365] | 1 | True | 0.62 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486877aa30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.3992s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 96.53 Core Time (ms) : 91.49 TIDL Subgraphs Processing Time (ms) : 91.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_898] | 0 | - | 0.15 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458417480 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.04 Core Time (ms) : 1.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1443] | 0 | - | 0.20 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2f9bb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.91 Core Time (ms) : 1.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_530] | 0 | - | 0.42 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb208b1d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.68 Core Time (ms) : 18.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1553] | 1 | True | 0.33 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f971de0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1492s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.85 Core Time (ms) : 7.41 TIDL Subgraphs Processing Time (ms) : 7.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1187] | 0 | - | 0.22 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45841a2d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1332] | 0 | - | 0.17 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b7ec90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_490] | 1 | True | 5.44 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2fa6a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3646s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060195041117528025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1043.73 Core Time (ms) : 974.37 TIDL Subgraphs Processing Time (ms) : 962.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 778891509 bytes MEM: Free's : 26 free's of 778891509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1808] | 0 | - | 0.47 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1022000 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.25 Core Time (ms) : 12.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_461] | 0 | - | 0.19 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a046020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1930] | 1 | True | 0.35 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492651920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2610s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.11 Core Time (ms) : 12.64 TIDL Subgraphs Processing Time (ms) : 12.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1843] | 0 | - | 1.74 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b95b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 81.89 Core Time (ms) : 81.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_634] | 0 | - | 0.51 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b19cb40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 113.69 Core Time (ms) : 113.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_195] | 0 | - | 1.46 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0903d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 80.05 Core Time (ms) : 80.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_278] | 1 | True | 0.61 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39750b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1550s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.27 Core Time (ms) : 48.13 TIDL Subgraphs Processing Time (ms) : 48.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_197] | 0 | - | 0.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ab925d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.08 Core Time (ms) : 2.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_869] | 0 | - | 0.22 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458502700 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.37 Core Time (ms) : 7.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1543] | 0 | - | 0.19 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c670c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.34 Core Time (ms) : 5.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_315] | 0 | - | 0.19 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd52950 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.84 Core Time (ms) : 0.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1072] | 1 | True | 0.24 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638ae7e10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.00 Core Time (ms) : 3.93 TIDL Subgraphs Processing Time (ms) : 3.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_429] | 0 | - | 0.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f88a5f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1749] | 0 | - | 0.17 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56752995e820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1557] | 0 | - | 0.15 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f5d5d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1156] | 0 | - | 2.12 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb208cc10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 100.55 Core Time (ms) : 100.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_888] | 0 | - | 3.79 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486877c3a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 61.64 Core Time (ms) : 61.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_663] | 0 | - | 0.14 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac7ca40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1041] | 1 | True | 0.18 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b7e770 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.173s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.88 Core Time (ms) : 0.75 TIDL Subgraphs Processing Time (ms) : 0.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1315] | 0 | - | 0.37 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585037a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.43 Core Time (ms) : 8.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_263] | 0 | - | 0.38 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd53f00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.62 Core Time (ms) : 5.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1008] | 0 | - | 0.62 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d200c450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 52.68 Core Time (ms) : 52.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_687] | 0 | - | 0.67 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a047be0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.03 Core Time (ms) : 23.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_633] | 0 | - | 0.19 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56752995efa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_484] | 0 | - | 0.24 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492653390 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.11 Core Time (ms) : 8.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_369] | 0 | - | 0.69 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f975150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.41 Core Time (ms) : 27.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1753] | 0 | - | 0.25 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c3b100 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.59 Core Time (ms) : 0.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1710] | 0 | - | 1.19 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bd3680 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.31 Core Time (ms) : 27.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1845] | 0 | - | 2.79 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac7e310 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 415.11 Core Time (ms) : 415.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1060] | 0 | - | 0.38 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1022290 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.40 Core Time (ms) : 6.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1971] | 0 | - | 0.97 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c6a500 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.64 Core Time (ms) : 27.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1213] | 0 | - | 0.20 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b0b6010 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_874] | 0 | - | 0.21 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56752995fcf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_442] | 1 | True | 0.16 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492658440 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1647s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.31 Core Time (ms) : 5.28 TIDL Subgraphs Processing Time (ms) : 5.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1149] | 0 | - | 0.53 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d25200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.19 Core Time (ms) : 9.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1955] | 1 | True | 0.18 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45841b020 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4166s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.14097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.14207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.14256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.14282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.14310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.14338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.14380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14688s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.13 Core Time (ms) : 4.96 TIDL Subgraphs Processing Time (ms) : 4.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1427] | 0 | - | 0.09 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a388cc90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1312] | 0 | - | 1.90 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467a4df0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.02 Core Time (ms) : 12.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1372] | 1 | True | 0.65 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce3d820 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.143s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2052s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.72 Core Time (ms) : 39.18 TIDL Subgraphs Processing Time (ms) : 39.07 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_792] | 0 | - | 0.42 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b19ea80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.69 Core Time (ms) : 5.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1967] | 1 | True | 0.24 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529960920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.197s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.22 Core Time (ms) : 1.01 TIDL Subgraphs Processing Time (ms) : 0.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_303] | 0 | - | 2.61 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492656600 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 87.36 Core Time (ms) : 87.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_642] | 0 | - | 1.64 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3977c00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 37.83 Core Time (ms) : 37.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_452] | 0 | - | 0.17 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa3f1bd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_257] | 1 | True | 0.25 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f397b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.191s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6965s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.56 Core Time (ms) : 8.37 TIDL Subgraphs Processing Time (ms) : 8.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1561] | 0 | - | 0.83 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458505fe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 284.33 Core Time (ms) : 284.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_277] | 0 | - | 0.17 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4db280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.97 Core Time (ms) : 2.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_735] | 0 | - | 0.58 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d200cdd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 50.10 Core Time (ms) : 50.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_931] | 0 | - | 0.56 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a4cb10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.46 Core Time (ms) : 23.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1480] | 0 | - | 0.33 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a049a20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.98 Core Time (ms) : 8.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_58] | 1 | True | 0.25 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f975630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.161s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2606s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2610s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.04 Core Time (ms) : 3.28 TIDL Subgraphs Processing Time (ms) : 3.18 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1472] | 1 | True | 0.21 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1025040 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.161s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4688s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.16 Core Time (ms) : 6.42 TIDL Subgraphs Processing Time (ms) : 6.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_517] | 0 | - | 0.52 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fdff20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.39 Core Time (ms) : 19.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1217] | 0 | - | 0.35 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4dc1b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.08 Core Time (ms) : 1.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_772] | 0 | - | 0.35 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b19fb40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.57 Core Time (ms) : 1.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1632] | 0 | - | 1.93 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d263f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.88 Core Time (ms) : 20.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_627] | 0 | - | 0.16 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10a8bc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.83 Core Time (ms) : 8.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1612] | 0 | - | 1.73 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f977410 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 40.50 Core Time (ms) : 40.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1079] | 0 | - | 0.16 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a050a60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1875] | 0 | - | 1.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce40590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.99 Core Time (ms) : 21.99 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_756] | 1 | True | 4.05 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c6b050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.143s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006024893020889532 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1281.62 Core Time (ms) : 1187.12 TIDL Subgraphs Processing Time (ms) : 1180.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 964138421 bytes MEM: Free's : 26 free's of 964138421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_688] | 1 | True | 0.20 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f3e0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.213s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3028s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3032s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.12 Core Time (ms) : 1.76 TIDL Subgraphs Processing Time (ms) : 1.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1857] | 0 | - | 0.83 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4dd080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.97 Core Time (ms) : 16.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_439] | 0 | - | 0.14 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69fa7dd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_966] | 0 | - | 0.14 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f63620 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1348] | 0 | - | 0.11 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d200dfe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.64 Core Time (ms) : 0.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1534] | 0 | - | 0.94 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a4cdf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.16 Core Time (ms) : 16.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1870] | 0 | - | 0.88 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac60570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 39.87 Core Time (ms) : 39.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1527] | 0 | - | 1.48 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bd4bd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.32 Core Time (ms) : 15.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_202] | 1 | True | 0.96 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fe1190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.190s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3563s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 71.65 Core Time (ms) : 57.33 TIDL Subgraphs Processing Time (ms) : 57.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_188] | 1 | True | 0.50 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0925d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.203s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2881s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 55.26 Core Time (ms) : 50.97 TIDL Subgraphs Processing Time (ms) : 50.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1010] | 0 | - | 0.23 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d200ed50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.23 Core Time (ms) : 11.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1473] | 0 | - | 0.49 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1029dd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.39 Core Time (ms) : 1.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1162] | 0 | - | 0.20 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f631f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.10 Core Time (ms) : 18.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1864] | 0 | - | 0.35 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2b9ce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.85 Core Time (ms) : 4.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1098] | 0 | - | 0.34 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a04c740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.21 Core Time (ms) : 6.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_299] | 0 | - | 0.15 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f27510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_351] | 0 | - | 0.13 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d20195b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_470] | 0 | - | 0.98 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2bb8a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 33.58 Core Time (ms) : 33.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_651] | 0 | - | 0.49 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba102a160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.49 Core Time (ms) : 9.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_826] | 0 | - | 0.20 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69faa560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.10 Core Time (ms) : 1.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_241] | 1 | True | 0.79 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2010a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 66.78 Core Time (ms) : 52.39 TIDL Subgraphs Processing Time (ms) : 52.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_83] | 0 | - | 1.78 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a04d550 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 135.84 Core Time (ms) : 135.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1327] | 0 | - | 0.58 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb208d0a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 17.77 Core Time (ms) : 17.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_293] | 1 | True | 0.88 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4dd710 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.212s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10315s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10328s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012947927076668074 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 160.73 Core Time (ms) : 142.61 TIDL Subgraphs Processing Time (ms) : 142.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 154240021 bytes MEM: Free's : 26 free's of 154240021 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1538] | 0 | - | 0.20 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a094530 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.85 Core Time (ms) : 0.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_815] | 0 | - | 0.15 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3977e20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.53 Core Time (ms) : 0.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_247] | 0 | - | 0.70 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac60ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 53.64 Core Time (ms) : 53.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1188] | 0 | - | 0.16 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a539f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_843] | 0 | - | 0.46 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3978f20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 26.40 Core Time (ms) : 26.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1650] | 0 | - | 0.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd56e70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1689] | 0 | - | 0.14 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59214683a990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.58 Core Time (ms) : 0.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1121] | 1 | True | 0.31 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a098b30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.144s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.11803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.11839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.11881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.11919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.11953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.34 Core Time (ms) : 3.26 TIDL Subgraphs Processing Time (ms) : 3.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1952] | 0 | - | 0.14 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fe6d10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_119] | 0 | - | 0.22 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba102b6b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.56 Core Time (ms) : 1.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_364] | 0 | - | 0.27 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce40fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.33 Core Time (ms) : 1.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1551] | 0 | - | 0.26 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a4e3f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1889] | 0 | - | 0.21 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466bc9e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.69 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1085] | 0 | - | 0.18 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fe4720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.66 Core Time (ms) : 0.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_920] | 0 | - | 15.96 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba102b180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5226.78 Core Time (ms) : 5226.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1577] | 0 | - | 0.19 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69fadad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.53 Core Time (ms) : 7.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1233] | 0 | - | 0.57 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb208e140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.14 Core Time (ms) : 10.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1727] | 0 | - | 0.11 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812efaf00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.85 Core Time (ms) : 0.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1592] | 1 | True | 0.48 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467a7280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.173s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.35 Core Time (ms) : 29.46 TIDL Subgraphs Processing Time (ms) : 29.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_150] | 1 | True | 2.85 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce41d40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060112036577703665 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 531.92 Core Time (ms) : 391.38 TIDL Subgraphs Processing Time (ms) : 389.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 356725613 bytes MEM: Free's : 26 free's of 356725613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_993] | 1 | True | 0.21 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a4fc10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.161s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2074s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2077s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.65 Core Time (ms) : 5.59 TIDL Subgraphs Processing Time (ms) : 5.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1752] | 0 | - | 1.24 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2012020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.22 Core Time (ms) : 23.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1124] | 0 | - | 0.31 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9783e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.55 Core Time (ms) : 8.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_908] | 0 | - | 0.23 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3890340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1370] | 0 | - | 0.75 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fe5f30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.06 Core Time (ms) : 10.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1144] | 0 | - | 0.99 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bd4d10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.24 Core Time (ms) : 25.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1244] | 0 | - | 0.59 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2bb2b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.35 Core Time (ms) : 6.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_536] | 0 | - | 42.27 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0981f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1297.67 Core Time (ms) : 1297.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_212] | 0 | - | 0.63 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d272f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.77 Core Time (ms) : 5.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_766] | 0 | - | 0.36 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a51e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.89 Core Time (ms) : 2.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_289] | 0 | - | 0.58 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac61c90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.47 Core Time (ms) : 13.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1380] | 0 | - | 0.29 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458548650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 84.07 Core Time (ms) : 84.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1045] | 0 | - | 1.08 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac7f4a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 259.16 Core Time (ms) : 259.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1512] | 0 | - | 0.53 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4dffc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.20 Core Time (ms) : 4.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1366] | 0 | - | 0.42 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a38906e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.04 Core Time (ms) : 4.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_934] | 0 | - | 2.04 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f979bf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 51.46 Core Time (ms) : 51.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_657] | 0 | - | 0.08 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492661590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1706] | 0 | - | 1.38 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467a8da0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.48 Core Time (ms) : 16.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1958] | 0 | - | 0.17 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549265abc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_504] | 1 | True | 0.33 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458549d70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.147s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.96 Core Time (ms) : 27.79 TIDL Subgraphs Processing Time (ms) : 27.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_972] | 0 | - | 0.79 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb208f520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.10 Core Time (ms) : 19.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1629] | 0 | - | 1.53 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a52510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.45 Core Time (ms) : 20.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_602] | 0 | - | 0.93 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492658e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 48.90 Core Time (ms) : 48.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_842] | 0 | - | 0.29 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2bc2b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.50 Core Time (ms) : 1.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_729] | 0 | - | 3.91 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a397aac0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1620.06 Core Time (ms) : 1620.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1497] | 0 | - | 1.31 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d27850 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 43.29 Core Time (ms) : 43.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1667] | 0 | - | 0.22 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa3f83f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.56 Core Time (ms) : 0.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_639] | 0 | - | 0.18 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab791c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.26 Core Time (ms) : 0.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_82] | 0 | - | 1.00 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fe6630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.45 Core Time (ms) : 25.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1214] | 0 | - | 0.15 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45854c330 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.51 Core Time (ms) : 2.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_544] | 0 | - | 16.96 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac644c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 470.71 Core Time (ms) : 470.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_928] | 1 | True | 0.78 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2bcce0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.166s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.98 Core Time (ms) : 37.54 TIDL Subgraphs Processing Time (ms) : 37.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_334] | 0 | - | 0.27 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa3f74e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.89 Core Time (ms) : 20.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_930] | 1 | True | 0.17 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458464140 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.228s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.43 Core Time (ms) : 2.01 TIDL Subgraphs Processing Time (ms) : 1.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1215] | 0 | - | 0.87 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a04ddc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.19 Core Time (ms) : 5.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1505] | 0 | - | 0.08 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868694160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.75 Core Time (ms) : 0.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1287] | 0 | - | 0.17 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638aef5e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1828] | 0 | - | 0.83 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486877d770 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.57 Core Time (ms) : 21.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1102] | 0 | - | 0.52 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458550720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 326.39 Core Time (ms) : 326.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1091] | 1 | True | 0.31 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638aedd60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.139s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2223s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2226s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.03 Core Time (ms) : 2.85 TIDL Subgraphs Processing Time (ms) : 2.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1815] | 0 | - | 1.04 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2013190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 50.88 Core Time (ms) : 50.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_830] | 0 | - | 2.40 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4e21d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1441.61 Core Time (ms) : 1441.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1770] | 1 | True | 0.30 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac7f4c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.154s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5795s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5799s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.80 Core Time (ms) : 13.72 TIDL Subgraphs Processing Time (ms) : 13.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1716] | 1 | True | 0.30 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2090210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.156s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2658s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2660s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.03 Core Time (ms) : 8.03 TIDL Subgraphs Processing Time (ms) : 7.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1281] | 0 | - | 0.46 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bd8d60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.09 Core Time (ms) : 13.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_251] | 1 | True | 0.51 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492659e90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4060s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4068s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 45.09 Core Time (ms) : 25.04 TIDL Subgraphs Processing Time (ms) : 24.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1223] | 0 | - | 0.65 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac82940 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.34 Core Time (ms) : 22.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_950] | 1 | True | 0.27 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1faad80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.185s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7228s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7238s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.66 Core Time (ms) : 0.58 TIDL Subgraphs Processing Time (ms) : 0.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12970373 bytes MEM: Free's : 26 free's of 12970373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1898] | 0 | - | 0.19 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458550a00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.25 Core Time (ms) : 3.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_847] | 0 | - | 0.35 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2beb00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.09 Core Time (ms) : 15.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_776] | 0 | - | 3.33 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fe7220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 70.51 Core Time (ms) : 70.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1262] | 1 | True | 0.45 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467aac40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 35.93 Core Time (ms) : 32.87 TIDL Subgraphs Processing Time (ms) : 32.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_139] | 0 | - | 0.57 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2094e70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.80 Core Time (ms) : 8.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1756] | 0 | - | 0.08 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584686b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_656] | 0 | - | 1.63 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a04e570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 47.39 Core Time (ms) : 47.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_37] | 0 | - | 0.28 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486877ec30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.08 Core Time (ms) : 18.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1777] | 0 | - | 0.19 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458552570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.46 Core Time (ms) : 1.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1846] | 0 | - | 0.45 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d286d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.55 Core Time (ms) : 16.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_545] | 0 | - | 0.24 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5675299699e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.21 Core Time (ms) : 1.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_521] | 0 | - | 0.16 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549265c130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.36 Core Time (ms) : 2.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1537] | 0 | - | 0.49 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bda270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.70 Core Time (ms) : 7.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_694] | 0 | - | 0.11 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1d5ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1275] | 0 | - | 0.19 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458554570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.84 Core Time (ms) : 1.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1368] | 0 | - | 0.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2c0350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.41 Core Time (ms) : 7.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_344] | 0 | - | 0.25 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486877ee00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.53 Core Time (ms) : 1.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1674] | 0 | - | 0.23 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549265cdb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.46 Core Time (ms) : 11.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1552] | 1 | True | 0.30 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac82f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13503s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.78 Core Time (ms) : 17.82 TIDL Subgraphs Processing Time (ms) : 17.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1429] | 0 | - | 1.05 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467abf50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 766.83 Core Time (ms) : 766.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_413] | 0 | - | 0.22 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f2b7d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1384] | 0 | - | 0.39 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a53cc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 58.32 Core Time (ms) : 58.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_686] | 1 | True | 0.45 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2fd630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2118s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2120s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.00 Core Time (ms) : 14.64 TIDL Subgraphs Processing Time (ms) : 14.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1347] | 0 | - | 0.14 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45846ac50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_964] | 0 | - | 0.49 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f97a890 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.01 Core Time (ms) : 4.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_177] | 0 | - | 0.13 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2095da0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1957] | 0 | - | 0.47 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c6c8f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.02 Core Time (ms) : 8.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1779] | 0 | - | 0.07 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492574020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.26 Core Time (ms) : 0.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_493] | 0 | - | 0.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486877ff50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.82 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_332] | 0 | - | 0.23 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c402c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1979] | 0 | - | 0.58 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2015050 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.17 Core Time (ms) : 14.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_714] | 0 | - | 0.11 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2c6630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_753] | 0 | - | 1.60 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458554fc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 111.79 Core Time (ms) : 111.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1150] | 0 | - | 0.64 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac84ed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 48.91 Core Time (ms) : 48.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1343] | 1 | True | 0.71 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354925744d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.177s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513113e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 74.94 Core Time (ms) : 71.50 TIDL Subgraphs Processing Time (ms) : 71.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50492469 bytes MEM: Free's : 26 free's of 50492469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_52] | 0 | - | 1.28 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2096a20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.23 Core Time (ms) : 20.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_620] | 0 | - | 0.41 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bda990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.22 Core Time (ms) : 6.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_587] | 1 | True | 0.82 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2c1680 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.193s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8910s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8920s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013912426325924823 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 88.14 Core Time (ms) : 72.71 TIDL Subgraphs Processing Time (ms) : 72.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83724677 bytes MEM: Free's : 26 free's of 83724677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_292] | 0 | - | 0.17 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a53e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1066] | 0 | - | 0.43 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687803a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.69 Core Time (ms) : 13.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1963] | 1 | True | 0.25 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d2e350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7955s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.22 Core Time (ms) : 5.19 TIDL Subgraphs Processing Time (ms) : 5.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1117] | 0 | - | 0.17 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce43ee0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.97 Core Time (ms) : 8.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_228] | 0 | - | 0.57 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2feeb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 218.29 Core Time (ms) : 218.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_581] | 0 | - | 0.31 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a547b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.43 Core Time (ms) : 13.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1568] | 1 | True | 0.18 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9846d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.34 Core Time (ms) : 4.30 TIDL Subgraphs Processing Time (ms) : 4.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12478853 bytes MEM: Free's : 26 free's of 12478853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_673] | 0 | - | 0.24 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b0f8e60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1322] | 0 | - | 0.22 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b84370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1653] | 1 | True | 0.31 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce45420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.148s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2248s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2251s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.90 Core Time (ms) : 11.58 TIDL Subgraphs Processing Time (ms) : 11.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_451] | 0 | - | 0.19 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c43400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1199] | 0 | - | 0.27 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bdbb50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.26 Core Time (ms) : 6.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_534] | 1 | True | 0.24 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f97c080 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.25 Core Time (ms) : 5.60 TIDL Subgraphs Processing Time (ms) : 5.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1253] | 0 | - | 0.47 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2015000 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.10 Core Time (ms) : 16.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1844] | 0 | - | 0.84 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1e42a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 39.88 Core Time (ms) : 39.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1176] | 0 | - | 0.14 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868699580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1349] | 0 | - | 0.20 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c44880 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.38 Core Time (ms) : 1.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_444] | 0 | - | 0.11 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac84f10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.54 Core Time (ms) : 1.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_595] | 0 | - | 0.93 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a55ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 379.58 Core Time (ms) : 379.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1789] | 0 | - | 0.21 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b85f20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_41] | 0 | - | 0.61 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926600d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.36 Core Time (ms) : 22.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_770] | 0 | - | 0.24 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bdc720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.84 Core Time (ms) : 1.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1456] | 0 | - | 1.07 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce46a90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 465.23 Core Time (ms) : 465.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_677] | 0 | - | 0.93 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868781a70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 34.43 Core Time (ms) : 34.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_250] | 0 | - | 1.04 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac85c50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 85.02 Core Time (ms) : 85.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_668] | 0 | - | 0.39 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f97eb20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.15 Core Time (ms) : 15.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_828] | 0 | - | 0.92 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467acb30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.48 Core Time (ms) : 25.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_924] | 0 | - | 1.00 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2ff560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 653.81 Core Time (ms) : 653.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1388] | 0 | - | 0.26 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c44c50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.42 Core Time (ms) : 1.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_27] | 0 | - | 0.72 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b85510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.78 Core Time (ms) : 18.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_50] | 0 | - | 0.09 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1d9ed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1981] | 0 | - | 0.87 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a04ec80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 340.02 Core Time (ms) : 340.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_203] | 0 | - | 0.39 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bdca00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.87 Core Time (ms) : 8.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_230] | 0 | - | 0.19 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2c4020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.15 Core Time (ms) : 3.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_416] | 1 | True | 0.40 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2015fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.181s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12426s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.89 Core Time (ms) : 18.06 TIDL Subgraphs Processing Time (ms) : 17.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1277] | 1 | True | 0.33 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4e31c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.174s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5742s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.52 Core Time (ms) : 13.14 TIDL Subgraphs Processing Time (ms) : 12.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_168] | 0 | - | 0.18 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d2efb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.69 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_508] | 1 | True | 0.39 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f894d60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.218s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3908s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0029605766221378117 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.40 Core Time (ms) : 45.67 TIDL Subgraphs Processing Time (ms) : 45.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50492469 bytes MEM: Free's : 26 free's of 50492469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1591] | 0 | - | 0.25 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2c5540 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.32 Core Time (ms) : 1.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1095] | 0 | - | 0.92 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d2f960 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 50.43 Core Time (ms) : 50.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_373] | 0 | - | 1.28 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2096b50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 34.61 Core Time (ms) : 34.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_553] | 0 | - | 0.76 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492660900 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.26 Core Time (ms) : 23.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_226] | 0 | - | 0.33 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bddf50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.30 Core Time (ms) : 8.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1122] | 0 | - | 30.59 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1e5400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10798.35 Core Time (ms) : 10798.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_989] | 0 | - | 0.69 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2017cf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 221.71 Core Time (ms) : 221.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_712] | 0 | - | 0.71 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4e5210 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.10 Core Time (ms) : 25.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_833] | 1 | True | 0.21 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2c5960 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.132s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4208s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.87 Core Time (ms) : 19.84 TIDL Subgraphs Processing Time (ms) : 19.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1460] | 0 | - | 0.32 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f980b30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.73 Core Time (ms) : 8.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_579] | 0 | - | 0.25 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45846c9c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.67 Core Time (ms) : 1.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1385] | 0 | - | 0.11 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a56a90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.62 Core Time (ms) : 0.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_890] | 0 | - | 0.31 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c6fd80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.97 Core Time (ms) : 1.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1759] | 0 | - | 0.12 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1dd020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.19 Core Time (ms) : 4.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_423] | 0 | - | 0.14 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868698b80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1535] | 0 | - | 0.89 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a571a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 26.04 Core Time (ms) : 26.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1184] | 0 | - | 0.12 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466c3ce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_636] | 1 | True | 0.16 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638af6950 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.87 Core Time (ms) : 3.78 TIDL Subgraphs Processing Time (ms) : 3.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12970373 bytes MEM: Free's : 26 free's of 12970373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_853] | 0 | - | 0.17 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2c8520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.19 Core Time (ms) : 1.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_525] | 1 | True | 0.50 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac864c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.15 Core Time (ms) : 30.65 TIDL Subgraphs Processing Time (ms) : 30.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_980] | 1 | True | 0.58 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458556470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2465s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2468s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 73.32 Core Time (ms) : 69.26 TIDL Subgraphs Processing Time (ms) : 69.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_473] | 0 | - | 0.71 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce471b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.04 Core Time (ms) : 15.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_665] | 0 | - | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc300160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.12 Core Time (ms) : 3.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_409] | 0 | - | 0.17 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486878d780 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1780] | 0 | - | 0.37 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a04fce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.24 Core Time (ms) : 1.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1170] | 1 | True | 0.38 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467ae010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.189s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2375s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.13 Core Time (ms) : 13.23 TIDL Subgraphs Processing Time (ms) : 13.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1906] | 0 | - | 0.41 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f982190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.01 Core Time (ms) : 16.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_270] | 0 | - | 0.15 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638be6c90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1270] | 0 | - | 0.40 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c6f990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.30 Core Time (ms) : 4.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1276] | 0 | - | 0.52 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2c8fe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 33.23 Core Time (ms) : 33.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_207] | 0 | - | 0.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868819970 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.97 Core Time (ms) : 0.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1164] | 0 | - | 0.18 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3891910 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.25 Core Time (ms) : 0.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_445] | 0 | - | 0.17 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638be0b00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.94 Core Time (ms) : 7.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_543] | 0 | - | 0.39 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc301630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.14 Core Time (ms) : 15.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1717] | 0 | - | 0.35 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492661cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.18 Core Time (ms) : 3.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_101] | 0 | - | 0.61 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2018ae0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.49 Core Time (ms) : 20.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_433] | 0 | - | 0.16 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa3fbff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.61 Core Time (ms) : 0.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_128] | 1 | True | 0.49 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a050400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2204s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2207s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.38 Core Time (ms) : 22.49 TIDL Subgraphs Processing Time (ms) : 22.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_845] | 0 | - | 0.38 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a38923f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.08 Core Time (ms) : 2.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_96] | 0 | - | 0.14 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638af8370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.56 Core Time (ms) : 0.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1352] | 0 | - | 0.33 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d31080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.82 Core Time (ms) : 11.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1822] | 0 | - | 0.39 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467b08a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.54 Core Time (ms) : 2.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_370] | 1 | True | 0.42 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868785af0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.141s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.29158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.29237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.29282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.29310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.29333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.29354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.29382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.29403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.29422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.29458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.29540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.29562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.29595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.29616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.29636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.29664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.29682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.29709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.29732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.29751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.29773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.29802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.29821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.29839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.29866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.29884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.29909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.29932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.29954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.29972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.29998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.30017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.30044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.30067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.30089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.30110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.30143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.30147s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.30151s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.12 Core Time (ms) : 10.62 TIDL Subgraphs Processing Time (ms) : 10.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_438] | 0 | - | 0.65 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac88b70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.01 Core Time (ms) : 20.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_940] | 0 | - | 0.32 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f898860 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.39 Core Time (ms) : 0.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1279] | 0 | - | 0.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c704a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_683] | 0 | - | 0.26 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4e5b20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.64 Core Time (ms) : 7.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_559] | 0 | - | 0.23 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638be2200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.81 Core Time (ms) : 2.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1703] | 1 | True | 0.28 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585587f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.76 Core Time (ms) : 12.06 TIDL Subgraphs Processing Time (ms) : 11.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1663] | 0 | - | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc3013e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.10 Core Time (ms) : 3.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1226] | 0 | - | 0.16 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492665ba0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1350] | 0 | - | 1.54 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2c9c60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 147.67 Core Time (ms) : 147.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1437] | 0 | - | 0.12 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd5e520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_281] | 0 | - | 0.38 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c70da0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 95.07 Core Time (ms) : 95.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_161] | 0 | - | 0.76 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d30e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 35.68 Core Time (ms) : 35.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_156] | 0 | - | 0.33 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4e72d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.82 Core Time (ms) : 6.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1801] | 0 | - | 0.38 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fe80f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.32 Core Time (ms) : 1.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_578] | 0 | - | 0.52 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2097d00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.08 Core Time (ms) : 9.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_623] | 0 | - | 0.41 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a572d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 48.04 Core Time (ms) : 48.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_558] | 1 | True | 0.36 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638be2ba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2076s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2079s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.03 Core Time (ms) : 15.52 TIDL Subgraphs Processing Time (ms) : 15.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_211] | 0 | - | 0.36 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a397cc00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.27 Core Time (ms) : 6.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1575] | 0 | - | 0.35 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f899110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 114.73 Core Time (ms) : 114.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_658] | 0 | - | 0.34 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467b0e90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.69 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1530] | 0 | - | 0.37 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492662650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.26 Core Time (ms) : 1.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1566] | 0 | - | 0.28 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486869c8a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_328] | 1 | True | 0.35 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce4ca60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7195s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.83 Core Time (ms) : 4.79 TIDL Subgraphs Processing Time (ms) : 4.72 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_427] | 0 | - | 0.31 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc302100 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.72 Core Time (ms) : 0.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1724] | 0 | - | 6.41 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45855ad40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 112.73 Core Time (ms) : 112.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1463] | 0 | - | 1.17 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a052240 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.59 Core Time (ms) : 14.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1502] | 0 | - | 11.68 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2019cc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 124.31 Core Time (ms) : 124.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_232] | 0 | - | 0.34 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4e7580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.46 Core Time (ms) : 14.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_816] | 0 | - | 0.41 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c71c50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.65 Core Time (ms) : 21.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1910] | 0 | - | 0.31 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687878f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.64 Core Time (ms) : 6.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_710] | 0 | - | 0.31 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac89740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.90 Core Time (ms) : 1.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1565] | 0 | - | 0.27 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812effb30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_537] | 0 | - | 0.29 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f984510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.92 Core Time (ms) : 2.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1017] | 1 | True | 0.49 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467b16e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.84 Core Time (ms) : 11.75 TIDL Subgraphs Processing Time (ms) : 11.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1362] | 0 | - | 2.16 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc304030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 90.79 Core Time (ms) : 90.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_295] | 0 | - | 0.28 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638be8d50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_719] | 0 | - | 2.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a397d9b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.02 Core Time (ms) : 12.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1996] | 0 | - | 0.50 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492663850 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.26 Core Time (ms) : 2.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1804] | 0 | - | 0.48 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce4aed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.74 Core Time (ms) : 18.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1943] | 0 | - | 13.10 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a581a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 623.19 Core Time (ms) : 623.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1337] | 0 | - | 0.42 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2099190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.67 Core Time (ms) : 1.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_974] | 0 | - | 0.66 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812feb080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 24.15 Core Time (ms) : 24.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1141] | 0 | - | 0.65 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4e8200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.49 Core Time (ms) : 27.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1649] | 1 | True | 0.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486869ffb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8157s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013782182165988901 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.51 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12970373 bytes MEM: Free's : 26 free's of 12970373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1414] | 0 | - | 0.23 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000aba0d30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_276] | 1 | True | 0.54 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638be59c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.140s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.29 Core Time (ms) : 18.67 TIDL Subgraphs Processing Time (ms) : 18.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1247] | 0 | - | 0.57 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9851a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 28.62 Core Time (ms) : 28.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_107] | 1 | True | 0.40 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d31ca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.143s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5761s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5765s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.77 Core Time (ms) : 29.81 TIDL Subgraphs Processing Time (ms) : 29.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_979] | 0 | - | 2.53 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c73330 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 710.44 Core Time (ms) : 710.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1142] | 1 | True | 3.27 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467b36f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013933627009714482 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 317.80 Core Time (ms) : 258.93 TIDL Subgraphs Processing Time (ms) : 258.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 253917013 bytes MEM: Free's : 26 free's of 253917013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_526] | 0 | - | 0.33 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486878a5c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.67 Core Time (ms) : 10.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_669] | 0 | - | 0.25 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000aba3240 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1624] | 1 | True | 4.60 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce4bc10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.162s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2182s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2187s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013933125081359568 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 300.86 Core Time (ms) : 248.80 TIDL Subgraphs Processing Time (ms) : 247.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 539593317 bytes MEM: Free's : 26 free's of 539593317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_339] | 0 | - | 0.25 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549257a8c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_727] | 0 | - | 3.42 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb209a280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 46.90 Core Time (ms) : 46.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1367] | 0 | - | 0.27 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d33d40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.50 Core Time (ms) : 12.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_349] | 1 | True | 0.33 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac8bda0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.205s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6684s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.89 Core Time (ms) : 8.84 TIDL Subgraphs Processing Time (ms) : 8.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_85] | 0 | - | 1.50 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492664ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 35.27 Core Time (ms) : 35.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1852] | 0 | - | 0.16 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638be75c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.58 Core Time (ms) : 0.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_402] | 1 | True | 0.27 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f984ef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.169s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7048s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7056s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 13.74 Core Time (ms) : 11.27 TIDL Subgraphs Processing Time (ms) : 11.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_598] | 0 | - | 0.64 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a053690 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.57 Core Time (ms) : 2.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_864] | 0 | - | 0.42 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812feaf20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.28 Core Time (ms) : 1.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_134] | 1 | True | 0.25 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4ed400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.164s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.39 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1420] | 0 | - | 0.96 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638be8ad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 34.00 Core Time (ms) : 34.00 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_629] | 1 | True | 0.39 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d347d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.172s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11224s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11228s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.21 Core Time (ms) : 20.10 TIDL Subgraphs Processing Time (ms) : 20.01 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1760] | 0 | - | 2.57 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2ca920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 41.62 Core Time (ms) : 41.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1171] | 1 | True | 0.34 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000aba3330 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.193s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10028s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.23 Core Time (ms) : 1.03 TIDL Subgraphs Processing Time (ms) : 0.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_606] | 0 | - | 0.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f990f40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1411] | 0 | - | 0.30 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4eac20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.20 Core Time (ms) : 16.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1842] | 0 | - | 0.17 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812febd50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.73 Core Time (ms) : 0.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1320] | 0 | - | 1.08 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9881e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.18 Core Time (ms) : 7.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1917] | 0 | - | 0.11 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d40c20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1442] | 0 | - | 0.32 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac8f490 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.86 Core Time (ms) : 22.86 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1900] | 0 | - | 2.38 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4eb150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 48.61 Core Time (ms) : 48.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1578] | 0 | - | 29.30 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fed100 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12907.12 Core Time (ms) : 12907.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1371] | 0 | - | 0.60 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d375b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.90 Core Time (ms) : 12.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_871] | 0 | - | 0.16 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f6a8d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_231] | 0 | - | 0.26 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a054d60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.58 Core Time (ms) : 1.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_437] | 1 | True | 0.15 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000aba6500 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.132s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.134s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4855s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.90 Core Time (ms) : 2.65 TIDL Subgraphs Processing Time (ms) : 2.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1925] | 0 | - | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638afff30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.21 Core Time (ms) : 2.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_769] | 0 | - | 0.15 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac923a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.36 Core Time (ms) : 1.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1919] | 1 | True | 0.32 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a056010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.164s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.45 Core Time (ms) : 6.81 TIDL Subgraphs Processing Time (ms) : 6.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1948] | 0 | - | 0.31 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac92ff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.59 Core Time (ms) : 2.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1433] | 0 | - | 0.43 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc303a80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.93 Core Time (ms) : 15.93 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1417] | 1 | True | 0.72 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c4ea30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513113e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.78 Core Time (ms) : 24.24 TIDL Subgraphs Processing Time (ms) : 24.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50492469 bytes MEM: Free's : 26 free's of 50492469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_759] | 0 | - | 0.67 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638be96d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 17.23 Core Time (ms) : 17.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_994] | 0 | - | 0.19 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3895440 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.60 Core Time (ms) : 0.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_248] | 0 | - | 0.13 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926657c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.74 Core Time (ms) : 0.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_752] | 1 | True | 0.57 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a056dc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9741s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 75.92 Core Time (ms) : 72.12 TIDL Subgraphs Processing Time (ms) : 71.97 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_728] | 0 | - | 0.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687d7360 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_855] | 1 | True | 0.22 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f98c1c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.142s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.15029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.15052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.15548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.15568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.15633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.15664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15800s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.75 Core Time (ms) : 0.71 TIDL Subgraphs Processing Time (ms) : 0.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_358] | 0 | - | 0.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926665e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.75 Core Time (ms) : 0.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_689] | 1 | True | 0.20 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3983ba0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2124s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2127s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.03 Core Time (ms) : 5.99 TIDL Subgraphs Processing Time (ms) : 5.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_542] | 1 | True | 0.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687ce360 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.27138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.27237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.27286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.27302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.27327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.27346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.27365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.27384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.27403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.27419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.27436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.27453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.27471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.27502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.27514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.27531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.27555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.27572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.27587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.27607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.27622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.27644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.27660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.27675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.27693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.27718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.27733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.27748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.27770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.27785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.27806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.27825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.27842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.27858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.27882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.27895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.27919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.27936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.27952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.27968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.27986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.27988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.27994s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.39 Core Time (ms) : 3.80 TIDL Subgraphs Processing Time (ms) : 3.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_932] | 0 | - | 0.24 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc304f00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.26 Core Time (ms) : 1.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_540] | 1 | True | 0.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549266b660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6976s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6980s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.47 Core Time (ms) : 3.43 TIDL Subgraphs Processing Time (ms) : 3.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_739] | 0 | - | 0.13 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3897110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1051] | 0 | - | 2.64 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f98ace0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 63.24 Core Time (ms) : 63.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_481] | 0 | - | 0.08 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687da820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_86] | 0 | - | 0.08 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687d6260 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_326] | 0 | - | 0.89 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3981e80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.88 Core Time (ms) : 10.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1089] | 0 | - | 0.58 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549257f850 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.65 Core Time (ms) : 8.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1406] | 0 | - | 0.54 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc304bf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 158.92 Core Time (ms) : 158.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1240] | 0 | - | 0.15 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000abedb60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.06 Core Time (ms) : 1.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_346] | 0 | - | 0.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638beb1e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.63 Core Time (ms) : 0.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_969] | 0 | - | 0.30 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848686e9940 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.14 Core Time (ms) : 2.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1441] | 0 | - | 2.00 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c73a60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 46.13 Core Time (ms) : 46.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_535] | 1 | True | 0.73 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d39c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5374s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5377s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 64.03 Core Time (ms) : 58.77 TIDL Subgraphs Processing Time (ms) : 58.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1178] | 0 | - | 0.74 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a059670 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.19 Core Time (ms) : 13.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_835] | 0 | - | 0.38 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acd7fb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.76 Core Time (ms) : 3.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1666] | 0 | - | 0.16 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b01ab0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.88 Core Time (ms) : 0.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1452] | 1 | True | 0.73 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848686ea4e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.168s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0029605766221378117 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 42.29 Core Time (ms) : 32.75 TIDL Subgraphs Processing Time (ms) : 32.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50492469 bytes MEM: Free's : 26 free's of 50492469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_141] | 0 | - | 0.14 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b02710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.95 Core Time (ms) : 0.95 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1713] | 0 | - | 0.13 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000abef8f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.68 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1569] | 0 | - | 0.28 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc306040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.10 Core Time (ms) : 6.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_561] | 0 | - | 0.14 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b03460 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.08 Core Time (ms) : 1.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_133] | 0 | - | 1.42 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492669cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.24 Core Time (ms) : 18.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_245] | 1 | True | 0.28 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acdac00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.160s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9834s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9837s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.42 Core Time (ms) : 4.63 TIDL Subgraphs Processing Time (ms) : 4.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1264] | 0 | - | 0.13 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b04160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.81 Core Time (ms) : 12.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_186] | 0 | - | 0.13 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2cb370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.59 Core Time (ms) : 0.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1238] | 0 | - | 0.33 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d3ba40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.14 Core Time (ms) : 9.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1829] | 0 | - | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0599f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.55 Core Time (ms) : 0.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_768] | 1 | True | 0.71 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39826d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.179s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2066s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2071s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.11 Core Time (ms) : 28.49 TIDL Subgraphs Processing Time (ms) : 28.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_615] | 1 | True | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc21d5d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13263s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13266s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.97 Core Time (ms) : 4.11 TIDL Subgraphs Processing Time (ms) : 4.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18240813 bytes MEM: Free's : 26 free's of 18240813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_806] | 0 | - | 2.78 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bee760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.47 Core Time (ms) : 14.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1671] | 1 | True | 0.23 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466cba80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012875171407235148 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.06 Core Time (ms) : 6.44 TIDL Subgraphs Processing Time (ms) : 6.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18240813 bytes MEM: Free's : 26 free's of 18240813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1934] | 0 | - | 3.33 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2cbfb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.78 Core Time (ms) : 16.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_322] | 1 | True | 0.24 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acdc7c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.223s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7628s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7638s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.12 Core Time (ms) : 6.46 TIDL Subgraphs Processing Time (ms) : 6.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31820165 bytes MEM: Free's : 26 free's of 31820165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1210] | 0 | - | 0.96 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a05af70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.69 Core Time (ms) : 13.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_333] | 0 | - | 0.38 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa402e70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.29 Core Time (ms) : 2.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1007] | 1 | True | 0.19 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687d6300 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.137s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7277s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7283s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.91 Core Time (ms) : 3.86 TIDL Subgraphs Processing Time (ms) : 3.77 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_378] | 0 | - | 0.73 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc307f90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.65 Core Time (ms) : 14.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1945] | 0 | - | 1.57 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d3c710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.98 Core Time (ms) : 20.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1579] | 1 | True | 0.40 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb209a780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.163s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4942s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.11 Core Time (ms) : 14.38 TIDL Subgraphs Processing Time (ms) : 14.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_505] | 0 | - | 1.53 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467b87f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.55 Core Time (ms) : 10.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1933] | 0 | - | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000abf4c80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_733] | 0 | - | 1.21 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687d7760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.02 Core Time (ms) : 10.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1586] | 0 | - | 3.13 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acdee50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 40.21 Core Time (ms) : 40.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1596] | 0 | - | 0.15 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4ecce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.88 Core Time (ms) : 0.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_562] | 1 | True | 7.94 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb209c8b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1953s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060195041117528025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 772.87 Core Time (ms) : 599.51 TIDL Subgraphs Processing Time (ms) : 591.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 778891509 bytes MEM: Free's : 26 free's of 778891509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_957] | 0 | - | 0.97 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3984050 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.41 Core Time (ms) : 19.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1762] | 1 | True | 1.04 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4ed050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545884 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 73.71 Core Time (ms) : 57.47 TIDL Subgraphs Processing Time (ms) : 57.30 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89076149 bytes MEM: Free's : 26 free's of 89076149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1402] | 1 | True | 0.18 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc21f860 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.189s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1952s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1956s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.10 Core Time (ms) : 5.78 TIDL Subgraphs Processing Time (ms) : 5.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1928] | 1 | True | 6.83 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a05b980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2281s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001392103241601961 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 500.51 Core Time (ms) : 366.55 TIDL Subgraphs Processing Time (ms) : 364.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 545339261 bytes MEM: Free's : 26 free's of 545339261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_720] | 0 | - | 3.11 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc30b270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 90.76 Core Time (ms) : 90.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_68] | 0 | - | 0.40 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549266aa60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.27 Core Time (ms) : 6.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_591] | 0 | - | 0.49 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c749f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.67 Core Time (ms) : 8.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_55] | 1 | True | 2.34 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce4cc50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013918601890109722 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 316.70 Core Time (ms) : 279.40 TIDL Subgraphs Processing Time (ms) : 278.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 205588549 bytes MEM: Free's : 26 free's of 205588549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1524] | 1 | True | 0.89 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549266b100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.155s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3927s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3935s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 101.25 Core Time (ms) : 92.41 TIDL Subgraphs Processing Time (ms) : 92.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_721] | 0 | - | 0.12 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8a3200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1951] | 0 | - | 0.66 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687d86d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 355.05 Core Time (ms) : 355.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1016] | 0 | - | 0.57 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39854e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.19 Core Time (ms) : 25.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_404] | 0 | - | 0.21 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c74b40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_909] | 0 | - | 0.18 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f98acd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_880] | 0 | - | 0.12 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4f2fa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1040] | 0 | - | 0.43 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467b8210 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.84 Core Time (ms) : 1.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_64] | 0 | - | 0.29 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c53ed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.27 Core Time (ms) : 1.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_10] | 0 | - | 0.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f98c4e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.70 Core Time (ms) : 0.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1735] | 0 | - | 0.27 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c75ff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.31 Core Time (ms) : 1.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1256] | 0 | - | 0.12 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4fa050 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_185] | 0 | - | 0.11 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4074d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_996] | 0 | - | 0.59 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f98d600 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.59 Core Time (ms) : 25.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_298] | 0 | - | 1.30 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d3e4f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 29.68 Core Time (ms) : 29.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_866] | 0 | - | 4.08 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4f1a00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 89.24 Core Time (ms) : 89.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1532] | 1 | True | 5.00 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c76560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.133s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4053s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00030963001383282337 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 456.24 Core Time (ms) : 345.25 TIDL Subgraphs Processing Time (ms) : 341.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 539593317 bytes MEM: Free's : 26 free's of 539593317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_857] | 0 | - | 0.43 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3985e50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.05 Core Time (ms) : 7.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1913] | 0 | - | 1.36 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467b91d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 50.27 Core Time (ms) : 50.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1081] | 0 | - | 4.99 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687da490 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 78.44 Core Time (ms) : 78.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_748] | 1 | True | 0.45 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45855c0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2019s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.58 Core Time (ms) : 21.65 TIDL Subgraphs Processing Time (ms) : 21.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_173] | 0 | - | 0.15 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354925859b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_239] | 0 | - | 0.70 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549266dea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.41 Core Time (ms) : 8.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1468] | 0 | - | 1.60 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39870e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.02 Core Time (ms) : 12.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1038] | 0 | - | 1.56 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f98db90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 38.47 Core Time (ms) : 38.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_238] | 0 | - | 0.13 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf4c40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1798] | 0 | - | 0.79 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45855d810 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.98 Core Time (ms) : 25.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1154] | 0 | - | 2.04 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638befd80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 52.02 Core Time (ms) : 52.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1627] | 0 | - | 0.27 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549266e240 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 67.72 Core Time (ms) : 67.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_75] | 1 | True | 0.29 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2cba80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.160s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7083s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7106s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.41 Core Time (ms) : 17.16 TIDL Subgraphs Processing Time (ms) : 16.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_659] | 1 | True | 0.21 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c55f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.72 Core Time (ms) : 3.29 TIDL Subgraphs Processing Time (ms) : 3.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1447] | 0 | - | 0.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492585af0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.25 Core Time (ms) : 0.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1638] | 0 | - | 0.11 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000abf5d40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.80 Core Time (ms) : 0.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1272] | 1 | True | 0.17 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467bd8d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5945s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.90 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_449] | 0 | - | 3.02 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45855e580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 31.97 Core Time (ms) : 31.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1800] | 0 | - | 0.08 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d45270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_256] | 1 | True | 0.19 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492586b50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10608s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.59 Core Time (ms) : 4.94 TIDL Subgraphs Processing Time (ms) : 4.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1454] | 0 | - | 1.03 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2cebe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.40 Core Time (ms) : 20.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1298] | 0 | - | 0.14 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ace0500 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.53 Core Time (ms) : 0.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_54] | 1 | True | 1.16 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce4ef50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.155s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8781s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8785s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210055 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 62.92 Core Time (ms) : 49.39 TIDL Subgraphs Processing Time (ms) : 48.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83724677 bytes MEM: Free's : 26 free's of 83724677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1291] | 0 | - | 0.88 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d418e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.52 Core Time (ms) : 9.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_412] | 0 | - | 1.30 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467bc070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 32.03 Core Time (ms) : 32.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1988] | 0 | - | 0.73 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ace15f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.50 Core Time (ms) : 22.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1504] | 0 | - | 0.14 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492677f10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.59 Core Time (ms) : 0.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1661] | 0 | - | 0.26 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492672340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.97 Core Time (ms) : 1.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1212] | 0 | - | 0.10 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2252f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_205] | 0 | - | 2.16 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f98ed70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 38.22 Core Time (ms) : 38.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1134] | 0 | - | 0.08 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a389de30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1682] | 0 | - | 2.05 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492672ee0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 59.28 Core Time (ms) : 59.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1794] | 0 | - | 2.18 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc30c8a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.69 Core Time (ms) : 15.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1820] | 0 | - | 3.29 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39882e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 106.78 Core Time (ms) : 106.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_510] | 1 | True | 0.21 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ace2cc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.146s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.15 Core Time (ms) : 8.17 TIDL Subgraphs Processing Time (ms) : 8.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_405] | 0 | - | 0.08 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d4a3f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_35] | 0 | - | 0.30 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d43720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.31 Core Time (ms) : 6.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_90] | 0 | - | 0.44 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2d0030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.04 Core Time (ms) : 2.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_368] | 0 | - | 0.43 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ace46f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 70.90 Core Time (ms) : 70.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1080] | 1 | True | 0.33 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce50ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.137s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5890s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5897s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.90 Core Time (ms) : 13.80 TIDL Subgraphs Processing Time (ms) : 13.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_913] | 0 | - | 0.36 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf07c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.16 Core Time (ms) : 10.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_219] | 1 | True | 0.21 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dc6ae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5936s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5949s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0059602946601225795 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.46 Core Time (ms) : 2.85 TIDL Subgraphs Processing Time (ms) : 2.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14964453 bytes MEM: Free's : 26 free's of 14964453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_155] | 1 | True | 3.21 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467bc270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.244s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7252s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001392103241601961 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 599.49 Core Time (ms) : 517.08 TIDL Subgraphs Processing Time (ms) : 514.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 545339261 bytes MEM: Free's : 26 free's of 545339261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_121] | 0 | - | 1.77 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2cfe00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.92 Core Time (ms) : 20.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_999] | 0 | - | 0.14 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000abfbe40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_509] | 1 | True | 1.54 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c5c210 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.82s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.84s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.10069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.10104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.10132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.10183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.10217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.10262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.10294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.10326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11259s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00030957406777050076 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 105.67 Core Time (ms) : 70.73 TIDL Subgraphs Processing Time (ms) : 70.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96616845 bytes MEM: Free's : 26 free's of 96616845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_147] | 0 | - | 1.43 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce52f40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 30.94 Core Time (ms) : 30.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_347] | 0 | - | 1.27 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf0730 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 38.63 Core Time (ms) : 38.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_775] | 0 | - | 0.14 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000abfc4a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.27 Core Time (ms) : 0.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_491] | 0 | - | 0.13 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000abfd080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1169] | 0 | - | 0.09 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000abfe1e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.65 Core Time (ms) : 0.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1487] | 0 | - | 1.23 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ace8ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 38.42 Core Time (ms) : 38.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1] | 1 | True | 0.44 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4f2780 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8495s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.86 Core Time (ms) : 44.29 TIDL Subgraphs Processing Time (ms) : 43.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1153] | 0 | - | 0.44 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926743d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.50 Core Time (ms) : 22.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_167] | 0 | - | 0.25 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f98f110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.86 Core Time (ms) : 1.86 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_701] | 0 | - | 0.17 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba102bc20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.88 Core Time (ms) : 0.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_666] | 0 | - | 0.14 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b07cf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.68 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1728] | 1 | True | 0.22 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458560050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5068s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5078s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.73 Core Time (ms) : 7.42 TIDL Subgraphs Processing Time (ms) : 7.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_235] | 0 | - | 1.91 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4f3880 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1240.81 Core Time (ms) : 1240.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_894] | 0 | - | 1.19 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce54130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 43.83 Core Time (ms) : 43.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_131] | 0 | - | 0.11 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b08870 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.21 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_31] | 0 | - | 0.32 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f43c90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.49 Core Time (ms) : 1.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_199] | 1 | True | 0.65 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492674180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.217s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 57.00 Core Time (ms) : 47.77 TIDL Subgraphs Processing Time (ms) : 47.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1006] | 0 | - | 0.43 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d470b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.43 Core Time (ms) : 5.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_466] | 0 | - | 0.24 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf2710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.85 Core Time (ms) : 1.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_465] | 0 | - | 0.32 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458477780 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.28 Core Time (ms) : 13.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1064] | 0 | - | 0.28 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2d08a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.90 Core Time (ms) : 8.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1139] | 0 | - | 0.27 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ace8a30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.26 Core Time (ms) : 15.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1974] | 0 | - | 0.14 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f43cc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1885] | 0 | - | 0.25 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf31b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.29 Core Time (ms) : 2.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1061] | 0 | - | 1.23 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c78460 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 53.52 Core Time (ms) : 53.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1771] | 0 | - | 0.16 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1032640 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_644] | 0 | - | 0.18 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458562220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.02 Core Time (ms) : 1.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_62] | 0 | - | 0.14 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2d5440 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_237] | 0 | - | 0.68 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d48f80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.78 Core Time (ms) : 5.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_630] | 1 | True | 0.22 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848686f1180 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.211s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7856s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.44 Core Time (ms) : 1.15 TIDL Subgraphs Processing Time (ms) : 1.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_533] | 1 | True | 0.25 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac00470 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8074s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8079s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00032368505410654264 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.52 Core Time (ms) : 2.71 TIDL Subgraphs Processing Time (ms) : 2.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15050965 bytes MEM: Free's : 26 free's of 15050965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_425] | 0 | - | 0.12 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf7f90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1340] | 1 | True | 0.39 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba102ed80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.140s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.18 Core Time (ms) : 29.18 TIDL Subgraphs Processing Time (ms) : 28.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_137] | 0 | - | 0.16 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2dc280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1074] | 0 | - | 0.95 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458562bb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 64.30 Core Time (ms) : 64.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1662] | 0 | - | 0.22 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492676f20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.79 Core Time (ms) : 1.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_568] | 1 | True | 0.58 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf4eb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545884 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 65.26 Core Time (ms) : 55.92 TIDL Subgraphs Processing Time (ms) : 55.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89076149 bytes MEM: Free's : 26 free's of 89076149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_605] | 0 | - | 0.92 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687dd450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.15 Core Time (ms) : 8.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1438] | 0 | - | 0.29 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2d2650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.98 Core Time (ms) : 1.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1737] | 0 | - | 0.95 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000aceb160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 33.87 Core Time (ms) : 33.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1009] | 0 | - | 0.11 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a38a1110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_157] | 0 | - | 0.21 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9d6e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_531] | 1 | True | 0.27 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492676f30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.180s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1881s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.39 Core Time (ms) : 11.76 TIDL Subgraphs Processing Time (ms) : 11.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1269] | 1 | True | 0.24 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2019e90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1535s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.66 Core Time (ms) : 2.96 TIDL Subgraphs Processing Time (ms) : 2.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1647] | 0 | - | 0.46 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1031a90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.20 Core Time (ms) : 10.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_685] | 0 | - | 0.10 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39917d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_862] | 0 | - | 2.26 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2d3f20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 73.66 Core Time (ms) : 73.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1887] | 0 | - | 2.94 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce54370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1095.75 Core Time (ms) : 1095.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_313] | 0 | - | 0.15 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9d3de0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.54 Core Time (ms) : 0.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1377] | 0 | - | 0.14 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3990590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_661] | 1 | True | 0.23 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516c5ee70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.177s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2457s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.57 Core Time (ms) : 6.33 TIDL Subgraphs Processing Time (ms) : 6.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_777] | 0 | - | 0.37 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a05d2b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.49 Core Time (ms) : 5.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_450] | 0 | - | 0.37 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492679850 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.37 Core Time (ms) : 9.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1003] | 1 | True | 0.39 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d201c550 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.189s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6742s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 44.60 Core Time (ms) : 36.09 TIDL Subgraphs Processing Time (ms) : 35.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1496] | 0 | - | 20.32 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a398a6d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 259.25 Core Time (ms) : 259.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_715] | 0 | - | 0.18 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bfbd60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1998] | 0 | - | 0.77 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9d5830 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 37.22 Core Time (ms) : 37.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1601] | 0 | - | 0.26 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d4ad00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.14 Core Time (ms) : 2.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1643] | 0 | - | 0.11 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f48960 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.52 Core Time (ms) : 0.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_60] | 0 | - | 0.40 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf6fa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.21 Core Time (ms) : 7.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_271] | 0 | - | 0.33 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a05df10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.58 Core Time (ms) : 1.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_329] | 0 | - | 0.11 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466d4e50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.86 Core Time (ms) : 0.86 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_225] | 0 | - | 1.71 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549267a780 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 49.27 Core Time (ms) : 49.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1813] | 0 | - | 5.44 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1032120 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 24.91 Core Time (ms) : 24.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1328] | 0 | - | 0.20 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f34b70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.74 Core Time (ms) : 19.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1285] | 1 | True | 0.37 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458562ee0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2046s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2048s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 23.86 Core Time (ms) : 15.88 TIDL Subgraphs Processing Time (ms) : 15.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1159] | 0 | - | 0.22 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687dd020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.09 Core Time (ms) : 1.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1111] | 0 | - | 12.00 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c78d30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3847.34 Core Time (ms) : 3847.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_290] | 1 | True | 0.23 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467c3c60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1456s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.68 Core Time (ms) : 6.64 TIDL Subgraphs Processing Time (ms) : 6.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1811] | 1 | True | 0.24 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d4b6e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7186s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7189s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.11 Core Time (ms) : 7.44 TIDL Subgraphs Processing Time (ms) : 7.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_57] | 0 | - | 0.10 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac049c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1407] | 0 | - | 0.41 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d201f490 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.19 Core Time (ms) : 2.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1039] | 0 | - | 0.68 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4f44a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.88 Core Time (ms) : 20.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1698] | 0 | - | 0.18 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac65130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.39 Core Time (ms) : 1.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_740] | 1 | True | 0.78 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb209f340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.160s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 81.36 Core Time (ms) : 74.27 TIDL Subgraphs Processing Time (ms) : 74.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1936] | 1 | True | 0.12 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a063080 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1543s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1546s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.24 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_74] | 0 | - | 0.10 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e8b00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_616] | 0 | - | 2.58 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000aced0c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 35.48 Core Time (ms) : 35.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1995] | 1 | True | 7.52 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467c0f20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.153s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2556s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013933125081359568 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 669.65 Core Time (ms) : 471.74 TIDL Subgraphs Processing Time (ms) : 469.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 539593317 bytes MEM: Free's : 26 free's of 539593317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_570] | 0 | - | 0.55 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf7a40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.85 Core Time (ms) : 2.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1819] | 1 | True | 0.59 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d4dcf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1620s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.89 Core Time (ms) : 45.79 TIDL Subgraphs Processing Time (ms) : 45.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1499] | 0 | - | 0.21 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45847b8d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.70 Core Time (ms) : 0.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1867] | 0 | - | 0.24 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687dee00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.71 Core Time (ms) : 0.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1172] | 0 | - | 0.24 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0613a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.15 Core Time (ms) : 1.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1228] | 1 | True | 0.22 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab7d270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.117s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.90 Core Time (ms) : 3.75 TIDL Subgraphs Processing Time (ms) : 3.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1888] | 0 | - | 0.15 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9d6160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.40 Core Time (ms) : 11.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_905] | 0 | - | 0.10 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458570200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1560] | 0 | - | 1.14 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d201f1d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.55 Core Time (ms) : 11.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_778] | 0 | - | 0.06 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e98c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1983] | 0 | - | 0.31 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9d7850 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.17 Core Time (ms) : 2.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_371] | 1 | True | 0.19 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f77df0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.51 Core Time (ms) : 4.34 TIDL Subgraphs Processing Time (ms) : 4.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1854] | 1 | True | 6.92 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac67390 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.183s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3413s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001392103241601961 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 490.29 Core Time (ms) : 376.69 TIDL Subgraphs Processing Time (ms) : 375.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 545339261 bytes MEM: Free's : 26 free's of 545339261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_153] | 1 | True | 0.30 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848686f7880 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1433s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012875171407235148 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.51 Core Time (ms) : 3.37 TIDL Subgraphs Processing Time (ms) : 3.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18240813 bytes MEM: Free's : 26 free's of 18240813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_741] | 0 | - | 0.25 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585669b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.25 Core Time (ms) : 1.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_33] | 0 | - | 0.65 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf95a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.80 Core Time (ms) : 7.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_574] | 1 | True | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f7a2f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1546s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00032368505410654264 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.48 Core Time (ms) : 1.32 TIDL Subgraphs Processing Time (ms) : 1.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15050965 bytes MEM: Free's : 26 free's of 15050965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1540] | 0 | - | 0.67 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d4eff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.92 Core Time (ms) : 14.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1127] | 0 | - | 0.07 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4f9390 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_566] | 0 | - | 0.54 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9d8700 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.31 Core Time (ms) : 3.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_872] | 1 | True | 0.54 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458568240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.165s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3054s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.75 Core Time (ms) : 48.10 TIDL Subgraphs Processing Time (ms) : 47.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1786] | 0 | - | 0.30 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa40bf70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.27 Core Time (ms) : 2.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_749] | 0 | - | 0.48 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e3070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.20 Core Time (ms) : 4.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_910] | 0 | - | 0.10 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f7ca50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_319] | 0 | - | 0.19 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20a13a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.54 Core Time (ms) : 0.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_965] | 1 | True | 0.18 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a5cb40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.200s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5059s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.64 Core Time (ms) : 0.60 TIDL Subgraphs Processing Time (ms) : 0.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_336] | 0 | - | 1.09 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0665c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.76 Core Time (ms) : 19.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_589] | 0 | - | 0.33 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a5a880 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.72 Core Time (ms) : 1.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_889] | 0 | - | 1.10 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20a1520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 66.00 Core Time (ms) : 66.00 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1863] | 1 | True | 0.24 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa40ba20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.138s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2161s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.10 Core Time (ms) : 0.93 TIDL Subgraphs Processing Time (ms) : 0.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1208] | 0 | - | 0.31 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e38f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.19 Core Time (ms) : 1.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_414] | 0 | - | 0.56 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9d9160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 35.56 Core Time (ms) : 35.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1718] | 1 | True | 0.73 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bf9630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6499s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 60.72 Core Time (ms) : 50.61 TIDL Subgraphs Processing Time (ms) : 50.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_187] | 0 | - | 0.13 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45847fa00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_569] | 0 | - | 1.62 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4f8440 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.20 Core Time (ms) : 12.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1986] | 0 | - | 0.30 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529971e00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.65 Core Time (ms) : 0.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1508] | 0 | - | 0.55 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d4fa10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.04 Core Time (ms) : 10.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1082] | 0 | - | 0.25 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45856a650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.86 Core Time (ms) : 5.86 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_649] | 0 | - | 1.33 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549267a1f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.08 Core Time (ms) : 21.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1681] | 0 | - | 0.14 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2d7d30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_454] | 0 | - | 1.12 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d201fc40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.76 Core Time (ms) : 23.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_174] | 0 | - | 0.48 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e38e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.34 Core Time (ms) : 15.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_343] | 0 | - | 0.36 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a5be60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.29 Core Time (ms) : 13.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1949] | 0 | - | 0.19 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45856bd40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.22 Core Time (ms) : 1.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_725] | 0 | - | 1.04 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2d4e60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 486.04 Core Time (ms) : 486.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_440] | 0 | - | 0.32 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc34f890 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.37 Core Time (ms) : 2.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_977] | 0 | - | 0.13 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8f0590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.58 Core Time (ms) : 0.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_432] | 1 | True | 2.82 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45856c4f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.210s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4013s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883466 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 119.56 Core Time (ms) : 86.13 TIDL Subgraphs Processing Time (ms) : 85.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 205588549 bytes MEM: Free's : 26 free's of 205588549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1806] | 0 | - | 0.25 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d501c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.42 Core Time (ms) : 1.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1836] | 0 | - | 0.14 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8f1510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1297] | 0 | - | 0.22 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a5c570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.92 Core Time (ms) : 5.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1135] | 0 | - | 16.59 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a066b00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 338.95 Core Time (ms) : 338.95 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_962] | 0 | - | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bfb050 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 72.27 Core Time (ms) : 72.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_472] | 0 | - | 0.13 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc356c80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.24 Core Time (ms) : 0.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1539] | 0 | - | 0.17 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e42c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.30 Core Time (ms) : 1.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_503] | 0 | - | 0.14 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20abf90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1546] | 0 | - | 0.11 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9dfd10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1522] | 1 | True | 0.83 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d51550 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.108s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1628s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1630s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012952854351498536 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.95 Core Time (ms) : 33.57 TIDL Subgraphs Processing Time (ms) : 33.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65231749 bytes MEM: Free's : 26 free's of 65231749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1094] | 1 | True | 2.95 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc351bb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.140s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2874s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031011005675458866 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 213.25 Core Time (ms) : 147.51 TIDL Subgraphs Processing Time (ms) : 141.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 292516277 bytes MEM: Free's : 26 free's of 292516277 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_300] | 0 | - | 1.26 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce55600 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 37.67 Core Time (ms) : 37.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_882] | 0 | - | 0.90 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a5dfe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.75 Core Time (ms) : 14.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_77] | 0 | - | 0.54 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bfc970 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 92.10 Core Time (ms) : 92.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_923] | 0 | - | 0.34 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9dca40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.10 Core Time (ms) : 2.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1992] | 0 | - | 0.46 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20a3730 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 17.22 Core Time (ms) : 17.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1265] | 0 | - | 0.38 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e4b30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.54 Core Time (ms) : 2.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_607] | 0 | - | 0.53 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9dddb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.04 Core Time (ms) : 7.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_391] | 0 | - | 11.41 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e59a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 210.21 Core Time (ms) : 210.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_567] | 0 | - | 0.49 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000aced910 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.45 Core Time (ms) : 6.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_12] | 1 | True | 0.40 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2020720 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.173s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1686s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.64 Core Time (ms) : 27.35 TIDL Subgraphs Processing Time (ms) : 27.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1087] | 0 | - | 0.42 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20a3540 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.27 Core Time (ms) : 13.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1422] | 0 | - | 0.15 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d36a5d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1978] | 1 | True | 0.22 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bfb7a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.145s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2147s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2150s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.59 Core Time (ms) : 6.72 TIDL Subgraphs Processing Time (ms) : 6.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1847] | 0 | - | 0.14 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492590690 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_66] | 1 | True | 0.24 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1ed480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.254s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.33 Core Time (ms) : 2.35 TIDL Subgraphs Processing Time (ms) : 2.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18240813 bytes MEM: Free's : 26 free's of 18240813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_495] | 0 | - | 2.36 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549267c790 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 37.04 Core Time (ms) : 37.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1083] | 0 | - | 1.23 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4f8be0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 34.42 Core Time (ms) : 34.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_897] | 0 | - | 2.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d53310 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 67.59 Core Time (ms) : 67.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1324] | 0 | - | 0.46 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bff0e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.73 Core Time (ms) : 1.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1288] | 1 | True | 0.20 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f38e50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4048s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513113e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.81 Core Time (ms) : 3.29 TIDL Subgraphs Processing Time (ms) : 3.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22128853 bytes MEM: Free's : 26 free's of 22128853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1619] | 0 | - | 0.37 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2d87c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.93 Core Time (ms) : 15.93 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_455] | 1 | True | 0.67 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acee910 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.208s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.10332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.06 Core Time (ms) : 32.82 TIDL Subgraphs Processing Time (ms) : 32.61 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1831] | 0 | - | 0.10 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8f5160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_761] | 0 | - | 1.76 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a5e270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.56 Core Time (ms) : 6.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_355] | 1 | True | 0.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fbb270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.168s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3501s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.75 Core Time (ms) : 1.50 TIDL Subgraphs Processing Time (ms) : 1.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1364] | 0 | - | 0.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8f5560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.32 Core Time (ms) : 1.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_302] | 1 | True | 2.51 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2024f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.211s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6185s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6189s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013918601890109722 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 135.55 Core Time (ms) : 98.22 TIDL Subgraphs Processing Time (ms) : 97.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 205588549 bytes MEM: Free's : 26 free's of 205588549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_459] | 1 | True | 1.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20a6c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.184s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10091s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10099s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 56.66 Core Time (ms) : 48.31 TIDL Subgraphs Processing Time (ms) : 48.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1878] | 0 | - | 0.95 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9dff10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.79 Core Time (ms) : 11.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_691] | 0 | - | 1.49 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638bff8b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 658.55 Core Time (ms) : 658.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1070] | 0 | - | 0.33 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce55590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.21 Core Time (ms) : 6.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1323] | 1 | True | 1.00 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2d8410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.173s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.9520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.9708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.9743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.9773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.21651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.21804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.21867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.21908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.21941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.21944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.21953s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.27 Core Time (ms) : 38.51 TIDL Subgraphs Processing Time (ms) : 38.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_583] | 0 | - | 0.83 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acf0950 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.30 Core Time (ms) : 2.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_709] | 0 | - | 2.56 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce56570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 91.36 Core Time (ms) : 91.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_596] | 0 | - | 0.73 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4fa2b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.74 Core Time (ms) : 18.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_160] | 1 | True | 0.16 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8f77e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6247s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.23 Core Time (ms) : 0.97 TIDL Subgraphs Processing Time (ms) : 0.92 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_891] | 0 | - | 0.20 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2dacc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.71 Core Time (ms) : 5.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_902] | 0 | - | 0.33 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20a7b20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.23 Core Time (ms) : 2.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1382] | 0 | - | 0.13 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8f98b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.16 Core Time (ms) : 0.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1197] | 0 | - | 0.12 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac07710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.32 Core Time (ms) : 0.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1024] | 0 | - | 0.12 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45856c580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.53 Core Time (ms) : 4.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_631] | 0 | - | 0.08 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2e1720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1519] | 0 | - | 0.60 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9e3cd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.37 Core Time (ms) : 11.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1296] | 0 | - | 0.12 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac07ae0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.92 Core Time (ms) : 0.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1317] | 1 | True | 11.91 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2dc740 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.157s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3270s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006024973541706476 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1196.52 Core Time (ms) : 1055.14 TIDL Subgraphs Processing Time (ms) : 1048.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1108566893 bytes MEM: Free's : 26 free's of 1108566893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_793] | 0 | - | 0.37 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45856e2c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.80 Core Time (ms) : 23.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_995] | 1 | True | 0.24 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac08fe0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.138s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3771s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3775s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.73 Core Time (ms) : 1.51 TIDL Subgraphs Processing Time (ms) : 1.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_408] | 0 | - | 0.56 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a5e660 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.87 Core Time (ms) : 12.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_361] | 0 | - | 0.28 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20a8ce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.64 Core Time (ms) : 0.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1077] | 0 | - | 0.24 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4fa290 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.07 Core Time (ms) : 2.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1758] | 0 | - | 0.23 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c007a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.03 Core Time (ms) : 2.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1163] | 0 | - | 0.24 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d542d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.04 Core Time (ms) : 6.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_755] | 0 | - | 0.47 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc354a40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.74 Core Time (ms) : 12.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_348] | 0 | - | 0.72 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acf46d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.17 Core Time (ms) : 14.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1428] | 0 | - | 0.53 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4fac90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.27 Core Time (ms) : 23.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1200] | 0 | - | 0.65 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20a90c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.00 Core Time (ms) : 27.00 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1598] | 0 | - | 0.85 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1032b30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 197.40 Core Time (ms) : 197.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1610] | 0 | - | 0.17 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458487390 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1432] | 0 | - | 0.67 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c00bf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.17 Core Time (ms) : 10.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_182] | 1 | True | 0.24 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d53290 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.49 Core Time (ms) : 10.43 TIDL Subgraphs Processing Time (ms) : 10.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_383] | 0 | - | 0.14 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354925927c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.37 Core Time (ms) : 6.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_483] | 0 | - | 0.26 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f8fba20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.24 Core Time (ms) : 2.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_214] | 0 | - | 0.50 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458570580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.70 Core Time (ms) : 6.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1325] | 0 | - | 0.58 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a5f810 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.87 Core Time (ms) : 11.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1973] | 0 | - | 0.57 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549267d060 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.88 Core Time (ms) : 12.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_959] | 0 | - | 0.18 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9e62d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.29 Core Time (ms) : 8.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1570] | 0 | - | 5.62 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc355050 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 63.24 Core Time (ms) : 63.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1161] | 1 | True | 0.17 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa410e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2106s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2110s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.77 Core Time (ms) : 1.45 TIDL Subgraphs Processing Time (ms) : 1.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1311] | 0 | - | 0.19 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9e75f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.65 Core Time (ms) : 1.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_717] | 0 | - | 1.61 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2026690 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 28.58 Core Time (ms) : 28.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1719] | 0 | - | 2.79 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20aa420 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 34.96 Core Time (ms) : 34.96 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_196] | 0 | - | 0.10 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa5015b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1435] | 0 | - | 1.21 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acf5210 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.06 Core Time (ms) : 15.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1434] | 0 | - | 0.35 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458570af0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.81 Core Time (ms) : 0.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1192] | 0 | - | 1.02 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c01b50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.99 Core Time (ms) : 20.99 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1684] | 1 | True | 7.71 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9e81f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.144s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6097s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001392103241601961 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 469.12 Core Time (ms) : 352.88 TIDL Subgraphs Processing Time (ms) : 350.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 545339261 bytes MEM: Free's : 26 free's of 545339261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_431] | 0 | - | 0.35 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4fee00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.01 Core Time (ms) : 2.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1923] | 0 | - | 0.19 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549267d780 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.55 Core Time (ms) : 0.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_306] | 1 | True | 0.25 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f49fb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.90 Core Time (ms) : 2.74 TIDL Subgraphs Processing Time (ms) : 2.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_229] | 1 | True | 0.31 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529975530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.145s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.26 Core Time (ms) : 2.05 TIDL Subgraphs Processing Time (ms) : 2.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_839] | 0 | - | 1.16 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549267ebd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.55 Core Time (ms) : 16.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_316] | 0 | - | 8.58 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458570b40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 102.54 Core Time (ms) : 102.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_116] | 0 | - | 0.81 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1035cc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.66 Core Time (ms) : 2.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1685] | 0 | - | 0.79 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa4ff1d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.69 Core Time (ms) : 7.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1241] | 1 | True | 0.95 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529a61a90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.133s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013912426325924823 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.60 Core Time (ms) : 39.10 TIDL Subgraphs Processing Time (ms) : 38.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83724677 bytes MEM: Free's : 26 free's of 83724677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1263] | 0 | - | 4.01 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce56dd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.76 Core Time (ms) : 23.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1042] | 0 | - | 4.87 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c02160 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 31.97 Core Time (ms) : 31.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_73] | 0 | - | 3.42 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acf5be0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 60.71 Core Time (ms) : 60.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1688] | 0 | - | 0.45 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa416990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 129.71 Core Time (ms) : 129.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1165] | 0 | - | 0.31 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1036b80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.56 Core Time (ms) : 1.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_381] | 0 | - | 0.17 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x56752997a440 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.71 Core Time (ms) : 0.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1232] | 0 | - | 6.28 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac69b10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3379.65 Core Time (ms) : 3379.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1491] | 0 | - | 0.16 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549267e310 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.66 Core Time (ms) : 0.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1792] | 0 | - | 6.45 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2027650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 75.15 Core Time (ms) : 75.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1849] | 0 | - | 2.64 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1037b50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 28.53 Core Time (ms) : 28.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_914] | 0 | - | 1.73 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492681ae0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 37.80 Core Time (ms) : 37.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_846] | 1 | True | 0.35 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467c2bc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.176s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5764s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5769s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.26 Core Time (ms) : 14.22 TIDL Subgraphs Processing Time (ms) : 14.09 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1449] | 0 | - | 0.23 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa417800 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.69 Core Time (ms) : 1.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_475] | 0 | - | 0.15 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa507b10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1415] | 0 | - | 0.62 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467c4540 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.29 Core Time (ms) : 7.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_784] | 0 | - | 0.64 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa501bc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.13 Core Time (ms) : 25.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_138] | 0 | - | 0.23 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467c5e10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.56 Core Time (ms) : 1.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1249] | 0 | - | 1.83 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa503660 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.59 Core Time (ms) : 22.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1490] | 0 | - | 0.12 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fc1840 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_881] | 0 | - | 2.21 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20ab700 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 37.91 Core Time (ms) : 37.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1821] | 1 | True | 0.95 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467c6410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.154s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2609s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 54.88 Core Time (ms) : 42.60 TIDL Subgraphs Processing Time (ms) : 42.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_282] | 0 | - | 0.09 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492595e10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_671] | 0 | - | 4.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492681070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1945.58 Core Time (ms) : 1945.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1705] | 1 | True | 0.76 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467c7fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.150s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6142s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.87 Core Time (ms) : 42.03 TIDL Subgraphs Processing Time (ms) : 41.93 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_744] | 0 | - | 1.10 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1037f90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.68 Core Time (ms) : 5.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1840] | 0 | - | 1.05 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce57250 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 637.57 Core Time (ms) : 637.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1207] | 1 | True | 0.30 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516d98750 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.74 Core Time (ms) : 34.63 TIDL Subgraphs Processing Time (ms) : 34.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1067] | 0 | - | 0.21 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa503560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.31 Core Time (ms) : 2.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1915] | 0 | - | 0.16 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acf7250 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.78 Core Time (ms) : 0.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1896] | 0 | - | 2.81 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467c9590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 39.54 Core Time (ms) : 39.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1482] | 0 | - | 0.08 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa419830 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1617] | 0 | - | 1.82 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acf75b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.63 Core Time (ms) : 19.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1937] | 1 | True | 0.20 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cb26f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.169s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2270s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.01 Core Time (ms) : 0.85 TIDL Subgraphs Processing Time (ms) : 0.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_916] | 0 | - | 0.26 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa41b390 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 32.47 Core Time (ms) : 32.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1914] | 0 | - | 0.15 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cb4ce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_42] | 1 | True | 0.35 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20ac380 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10122s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10131s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.83 Core Time (ms) : 29.50 TIDL Subgraphs Processing Time (ms) : 29.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1660] | 0 | - | 0.40 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa505b00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.50 Core Time (ms) : 14.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_693] | 0 | - | 0.30 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529aa6d30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.59 Core Time (ms) : 6.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1589] | 0 | - | 0.15 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cb5730 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.90 Core Time (ms) : 0.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_284] | 0 | - | 2.85 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10392a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 94.89 Core Time (ms) : 94.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1869] | 0 | - | 0.40 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc3568f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.84 Core Time (ms) : 6.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_365] | 0 | - | 0.13 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cb6300 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.33 Core Time (ms) : 0.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_21] | 0 | - | 0.79 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20ae8f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.66 Core Time (ms) : 11.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_901] | 0 | - | 0.19 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529aa9030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.44 Core Time (ms) : 5.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_821] | 1 | True | 0.51 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516da05d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.134s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7217s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.59 Core Time (ms) : 27.94 TIDL Subgraphs Processing Time (ms) : 27.76 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_941] | 1 | True | 0.99 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa506920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.244s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 59.62 Core Time (ms) : 34.79 TIDL Subgraphs Processing Time (ms) : 34.53 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_262] | 0 | - | 1.26 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce585a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 32.63 Core Time (ms) : 32.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_297] | 0 | - | 0.34 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529aa97c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.17 Core Time (ms) : 7.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1182] | 0 | - | 0.78 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc357790 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.46 Core Time (ms) : 21.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1903] | 0 | - | 0.15 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b192c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.89 Core Time (ms) : 4.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_61] | 0 | - | 0.17 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b90030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.83 Core Time (ms) : 0.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1112] | 0 | - | 1.55 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529aa9de0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 487.87 Core Time (ms) : 487.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1458] | 0 | - | 0.29 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516da3a10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.17 Core Time (ms) : 3.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_785] | 0 | - | 0.94 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c03ca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.36 Core Time (ms) : 7.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1132] | 0 | - | 2.46 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c7ab10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 130.93 Core Time (ms) : 130.93 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1763] | 0 | - | 0.18 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fc5870 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.09 Core Time (ms) : 1.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1926] | 0 | - | 1.51 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516da37f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 37.59 Core Time (ms) : 37.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1305] | 1 | True | 0.25 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fc6d90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2456s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.03 Core Time (ms) : 1.83 TIDL Subgraphs Processing Time (ms) : 1.67 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_988] | 0 | - | 0.16 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa5120a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1642] | 0 | - | 0.19 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc26dad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.83 Core Time (ms) : 1.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1880] | 0 | - | 0.27 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acf7c60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.41 Core Time (ms) : 1.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1313] | 0 | - | 0.20 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fc7f40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.77 Core Time (ms) : 0.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1564] | 1 | True | 0.65 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa5093e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 64.23 Core Time (ms) : 54.01 TIDL Subgraphs Processing Time (ms) : 53.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1026] | 0 | - | 0.41 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc3581a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.38 Core Time (ms) : 12.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1485] | 0 | - | 0.21 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd6eed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_586] | 0 | - | 0.72 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acf8e40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.93 Core Time (ms) : 16.93 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1405] | 1 | True | 6.47 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20b1ef0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.132s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16497s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16505s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003100000311834465 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 616.06 Core Time (ms) : 337.48 TIDL Subgraphs Processing Time (ms) : 334.68 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 964138421 bytes MEM: Free's : 26 free's of 964138421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1509] | 0 | - | 0.47 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c04900 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.28 Core Time (ms) : 11.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1220] | 0 | - | 0.48 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce59220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.50 Core Time (ms) : 11.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_9] | 0 | - | 0.54 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc35a400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.99 Core Time (ms) : 23.99 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_805] | 0 | - | 1.44 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa50a7c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 326.48 Core Time (ms) : 326.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_32] | 0 | - | 6.36 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467cb130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 243.26 Core Time (ms) : 243.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1585] | 0 | - | 0.73 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b1bbb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.70 Core Time (ms) : 15.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1032] | 0 | - | 1.56 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce5aad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.96 Core Time (ms) : 10.96 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_69] | 0 | - | 1.31 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529aab460 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.68 Core Time (ms) : 19.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1338] | 0 | - | 1.80 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492681aa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 557.36 Core Time (ms) : 557.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_990] | 0 | - | 0.37 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acf9520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.59 Core Time (ms) : 14.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_938] | 1 | True | 0.50 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc35adc0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.227s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3882s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 37.12 Core Time (ms) : 30.66 TIDL Subgraphs Processing Time (ms) : 30.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_960] | 0 | - | 1.39 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac6a980 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.32 Core Time (ms) : 15.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1173] | 0 | - | 0.84 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9e9910 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.57 Core Time (ms) : 20.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1227] | 0 | - | 0.97 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516da4340 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.28 Core Time (ms) : 20.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1891] | 0 | - | 0.35 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2027fb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.23 Core Time (ms) : 1.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_742] | 0 | - | 5.21 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acfa2f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 173.42 Core Time (ms) : 173.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1319] | 0 | - | 1.00 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e6850 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.24 Core Time (ms) : 12.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1174] | 0 | - | 0.48 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1039560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.12 Core Time (ms) : 12.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1922] | 1 | True | 0.62 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc35c260 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.198s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7573s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.62 Core Time (ms) : 13.83 TIDL Subgraphs Processing Time (ms) : 13.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_975] | 0 | - | 0.94 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c05ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.48 Core Time (ms) : 22.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_563] | 0 | - | 0.32 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f3f4f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.27 Core Time (ms) : 3.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1975] | 0 | - | 0.35 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c7ae10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.26 Core Time (ms) : 5.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1990] | 0 | - | 0.32 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f901350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.36 Core Time (ms) : 1.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1470] | 1 | True | 0.28 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f3ecb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1755s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.54 Core Time (ms) : 8.26 TIDL Subgraphs Processing Time (ms) : 8.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1479] | 0 | - | 0.19 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f52070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1701] | 0 | - | 0.25 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa50b430 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.74 Core Time (ms) : 0.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1697] | 0 | - | 0.19 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cbac60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_120] | 0 | - | 0.17 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2752c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_80] | 0 | - | 0.27 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f50a90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.08 Core Time (ms) : 3.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_885] | 0 | - | 0.18 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5675299c4e10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1520] | 0 | - | 0.16 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c82ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1375] | 0 | - | 2.28 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d202b190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1513.75 Core Time (ms) : 1513.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1559] | 0 | - | 0.20 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458487cc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.27 Core Time (ms) : 1.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_118] | 0 | - | 0.39 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9ebc20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.80 Core Time (ms) : 0.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1616] | 0 | - | 0.37 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516da70d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.58 Core Time (ms) : 2.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1334] | 0 | - | 1.55 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc35fd90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.67 Core Time (ms) : 11.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1129] | 0 | - | 3.02 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c7ce40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1648.98 Core Time (ms) : 1648.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_453] | 1 | True | 0.98 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa50d9e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013912426325924823 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 108.27 Core Time (ms) : 96.24 TIDL Subgraphs Processing Time (ms) : 95.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83724677 bytes MEM: Free's : 26 free's of 83724677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_754] | 1 | True | 4.66 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529aad9f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.219s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2973s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2979s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101944831958656 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 589.48 Core Time (ms) : 393.23 TIDL Subgraphs Processing Time (ms) : 391.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 545339261 bytes MEM: Free's : 26 free's of 545339261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_652] | 0 | - | 0.17 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd70aa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1747] | 0 | - | 5.53 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac6b8a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 299.67 Core Time (ms) : 299.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_780] | 0 | - | 3.12 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585727c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 26.66 Core Time (ms) : 26.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1113] | 0 | - | 2.97 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e6ee0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 98.31 Core Time (ms) : 98.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1704] | 0 | - | 3.11 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba103ba50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.50 Core Time (ms) : 21.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1186] | 0 | - | 0.20 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c05ad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.95 Core Time (ms) : 0.95 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1902] | 0 | - | 0.63 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce5c220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.39 Core Time (ms) : 13.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1230] | 0 | - | 7.03 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9ecab0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 254.39 Core Time (ms) : 254.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1118] | 0 | - | 0.69 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c077b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.89 Core Time (ms) : 10.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_460] | 0 | - | 0.27 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492598990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_554] | 0 | - | 0.65 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516da7430 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.46 Core Time (ms) : 4.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_522] | 0 | - | 1.10 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549259a3e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.19 Core Time (ms) : 18.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1436] | 0 | - | 0.43 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce5c380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.11 Core Time (ms) : 12.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1450] | 0 | - | 0.33 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa50f5b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.39 Core Time (ms) : 2.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_541] | 0 | - | 0.32 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cbe830 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.39 Core Time (ms) : 1.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_834] | 0 | - | 1.41 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c07b40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 72.21 Core Time (ms) : 72.21 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1730] | 0 | - | 0.33 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce5d1f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.48 Core Time (ms) : 23.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_488] | 0 | - | 0.22 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa516070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1515] | 1 | True | 0.70 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516da9120 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3835s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 124.57 Core Time (ms) : 102.02 TIDL Subgraphs Processing Time (ms) : 101.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_338] | 0 | - | 0.38 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc361380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.80 Core Time (ms) : 2.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1424] | 1 | True | 0.29 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa427340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.243s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2815s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2820s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.48 Core Time (ms) : 1.18 TIDL Subgraphs Processing Time (ms) : 1.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_676] | 0 | - | 0.19 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd73e20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.76 Core Time (ms) : 0.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_702] | 1 | True | 0.31 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1e6230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5333s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.70 Core Time (ms) : 9.62 TIDL Subgraphs Processing Time (ms) : 9.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1138] | 0 | - | 8.78 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2de630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 173.65 Core Time (ms) : 173.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1726] | 0 | - | 1.23 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492684620 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 34.66 Core Time (ms) : 34.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1503] | 0 | - | 0.38 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce5ed50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.67 Core Time (ms) : 7.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1203] | 0 | - | 0.37 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa513880 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.92 Core Time (ms) : 1.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_421] | 0 | - | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc3609c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.86 Core Time (ms) : 0.86 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1444] | 0 | - | 0.20 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b0ff230 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.49 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_527] | 1 | True | 0.36 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516daa230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.18 Core Time (ms) : 9.40 TIDL Subgraphs Processing Time (ms) : 9.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_443] | 1 | True | 1.80 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d202c4b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.153s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003100000311834461 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 136.06 Core Time (ms) : 94.83 TIDL Subgraphs Processing Time (ms) : 94.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 253917013 bytes MEM: Free's : 26 free's of 253917013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1225] | 1 | True | 0.27 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc3e3c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5437s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5449s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0059602946601225795 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.80 Core Time (ms) : 1.58 TIDL Subgraphs Processing Time (ms) : 1.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14964453 bytes MEM: Free's : 26 free's of 14964453 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_762] | 0 | - | 0.99 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1e97a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 24.01 Core Time (ms) : 24.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_851] | 0 | - | 0.42 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce5fcf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.43 Core Time (ms) : 6.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_45] | 0 | - | 0.48 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa513740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.27 Core Time (ms) : 11.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_104] | 0 | - | 0.22 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516db0b40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_321] | 0 | - | 0.18 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc367360 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1954] | 1 | True | 0.45 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c086a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5430s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.78 Core Time (ms) : 11.65 TIDL Subgraphs Processing Time (ms) : 11.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_385] | 0 | - | 0.19 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc36a4f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_164] | 1 | True | 0.49 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dad920 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.47s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.49s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4606s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 51.36 Core Time (ms) : 39.52 TIDL Subgraphs Processing Time (ms) : 39.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1410] | 0 | - | 0.29 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce5fc80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.74 Core Time (ms) : 12.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1609] | 1 | True | 0.60 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa513fa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.208s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 44.16 Core Time (ms) : 31.59 TIDL Subgraphs Processing Time (ms) : 31.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_675] | 0 | - | 0.19 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc27af70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.36 Core Time (ms) : 1.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_797] | 1 | True | 0.34 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c0a270 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5106s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.36 Core Time (ms) : 11.56 TIDL Subgraphs Processing Time (ms) : 11.28 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1658] | 0 | - | 0.15 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd76980 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.57 Core Time (ms) : 0.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_584] | 0 | - | 0.15 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549259acf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.72 Core Time (ms) : 0.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1331] | 1 | True | 0.25 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b92660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.177s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.54 Core Time (ms) : 2.15 TIDL Subgraphs Processing Time (ms) : 1.99 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_492] | 1 | True | 0.62 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc365520 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.253s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9812s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 68.02 Core Time (ms) : 50.08 TIDL Subgraphs Processing Time (ms) : 49.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1680] | 1 | True | 0.20 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848686fe140 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.171s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1728s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.69 Core Time (ms) : 2.47 TIDL Subgraphs Processing Time (ms) : 2.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1507] | 0 | - | 0.26 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce60e40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.18 Core Time (ms) : 1.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1620] | 0 | - | 0.25 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492685710 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.03 Core Time (ms) : 2.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_643] | 0 | - | 0.19 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cc5090 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_832] | 1 | True | 0.33 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1ea370 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.169s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1783s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1789s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.29 Core Time (ms) : 28.05 TIDL Subgraphs Processing Time (ms) : 27.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_730] | 1 | True | 0.46 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba103c610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5052s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 53.02 Core Time (ms) : 48.02 TIDL Subgraphs Processing Time (ms) : 47.63 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_789] | 0 | - | 0.74 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458573110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 161.42 Core Time (ms) : 161.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1255] | 0 | - | 5.64 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687e96c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 275.38 Core Time (ms) : 275.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1425] | 1 | True | 0.39 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c0e930 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.202s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.10 Core Time (ms) : 25.39 TIDL Subgraphs Processing Time (ms) : 25.10 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1830] | 0 | - | 0.20 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7b976a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1330] | 0 | - | 0.16 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cc61b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.04 Core Time (ms) : 18.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1344] | 0 | - | 4.40 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa515be0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2237.15 Core Time (ms) : 2237.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_807] | 0 | - | 0.21 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd7ae20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.67 Core Time (ms) : 0.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1848] | 0 | - | 1.12 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492686910 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.78 Core Time (ms) : 27.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_585] | 0 | - | 0.95 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fedc20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 17.95 Core Time (ms) : 17.95 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1775] | 0 | - | 0.20 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cc8ff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_971] | 0 | - | 2.14 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c80440 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 48.65 Core Time (ms) : 48.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_482] | 1 | True | 0.27 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1ed620 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.204s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2375s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.72 Core Time (ms) : 5.99 TIDL Subgraphs Processing Time (ms) : 5.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1439] | 0 | - | 0.38 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a067870 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.89 Core Time (ms) : 0.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1892] | 0 | - | 0.87 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce630f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.94 Core Time (ms) : 5.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1002] | 0 | - | 0.21 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c0fa40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.56 Core Time (ms) : 0.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1861] | 0 | - | 2.24 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba103e470 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 45.65 Core Time (ms) : 45.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_954] | 1 | True | 0.32 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc367f80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.195s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2326s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.70 Core Time (ms) : 5.44 TIDL Subgraphs Processing Time (ms) : 5.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1461] | 0 | - | 0.39 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516db20f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.31 Core Time (ms) : 1.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_512] | 0 | - | 1.61 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1ee860 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 34.55 Core Time (ms) : 34.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1767] | 1 | True | 5.25 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c107f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1569s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060195041117528025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 674.06 Core Time (ms) : 527.12 TIDL Subgraphs Processing Time (ms) : 524.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 778891509 bytes MEM: Free's : 26 free's of 778891509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_26] | 0 | - | 1.16 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d202d790 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 47.84 Core Time (ms) : 47.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1641] | 0 | - | 0.69 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585746d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.49 Core Time (ms) : 4.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1167] | 0 | - | 1.61 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a067d40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 26.44 Core Time (ms) : 26.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1031] | 0 | - | 0.35 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc280550 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.45 Core Time (ms) : 3.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_200] | 1 | True | 0.70 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acfaa10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 39.51 Core Time (ms) : 34.94 TIDL Subgraphs Processing Time (ms) : 34.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_401] | 0 | - | 0.28 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516ccaad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.08 Core Time (ms) : 2.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1123] | 0 | - | 0.44 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20b4060 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.67 Core Time (ms) : 5.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_129] | 0 | - | 0.26 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc281350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.03 Core Time (ms) : 1.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1897] | 0 | - | 0.92 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516db5470 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.57 Core Time (ms) : 6.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1218] | 1 | True | 0.29 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812f05410 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.139s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12441s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.17 Core Time (ms) : 0.97 TIDL Subgraphs Processing Time (ms) : 0.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1339] | 0 | - | 1.35 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce63180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 36.27 Core Time (ms) : 36.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_648] | 0 | - | 0.19 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549259f750 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_518] | 0 | - | 2.18 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc36a8c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 36.75 Core Time (ms) : 36.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_192] | 0 | - | 0.24 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45848b780 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.40 Core Time (ms) : 0.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_464] | 1 | True | 0.96 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529aaec50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.171s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1540s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1545s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013912426325924823 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 67.74 Core Time (ms) : 52.56 TIDL Subgraphs Processing Time (ms) : 52.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83724677 bytes MEM: Free's : 26 free's of 83724677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1533] | 1 | True | 0.24 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926867b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.151s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2134s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2137s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.69 Core Time (ms) : 4.97 TIDL Subgraphs Processing Time (ms) : 4.87 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_978] | 0 | - | 0.15 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466e16d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_619] | 0 | - | 0.21 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ff0e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.96 Core Time (ms) : 1.96 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1157] | 0 | - | 1.17 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20b67a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.85 Core Time (ms) : 19.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_827] | 0 | - | 0.97 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a398aeb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 44.59 Core Time (ms) : 44.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1097] | 1 | True | 0.41 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acfcc80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.234s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3476s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3480s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.35 Core Time (ms) : 6.60 TIDL Subgraphs Processing Time (ms) : 6.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_486] | 0 | - | 0.54 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467cd3e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 147.82 Core Time (ms) : 147.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_549] | 0 | - | 0.21 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45860b8c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.72 Core Time (ms) : 0.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1938] | 0 | - | 0.35 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812f08140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.56 Core Time (ms) : 1.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1959] | 1 | True | 0.50 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492689860 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.203s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9563s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9574s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.20 Core Time (ms) : 26.63 TIDL Subgraphs Processing Time (ms) : 26.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1333] | 0 | - | 0.43 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d202e900 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.80 Core Time (ms) : 5.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_375] | 0 | - | 0.25 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45848ea00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_942] | 0 | - | 1.08 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000acfdfc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 71.30 Core Time (ms) : 71.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_919] | 0 | - | 0.24 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812f088a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.77 Core Time (ms) : 1.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1621] | 0 | - | 0.84 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516db5000 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.48 Core Time (ms) : 20.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_804] | 0 | - | 0.43 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458576f80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.73 Core Time (ms) : 3.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_44] | 0 | - | 0.51 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1f0240 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.53 Core Time (ms) : 14.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_787] | 0 | - | 0.69 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467cc510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.42 Core Time (ms) : 14.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_844] | 0 | - | 0.38 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549268b830 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.48 Core Time (ms) : 1.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1501] | 0 | - | 0.37 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d202ed20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.22 Core Time (ms) : 1.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_162] | 0 | - | 0.31 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ff2820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.82 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1137] | 1 | True | 0.34 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab824f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.14 Core Time (ms) : 7.05 TIDL Subgraphs Processing Time (ms) : 7.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1185] | 0 | - | 0.16 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f7e020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1972] | 0 | - | 0.19 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5675299c64e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_746] | 1 | True | 0.29 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c80350 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.95 Core Time (ms) : 13.12 TIDL Subgraphs Processing Time (ms) : 13.05 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_91] | 0 | - | 2.57 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a398c8a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 97.52 Core Time (ms) : 97.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_398] | 0 | - | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a06d590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1654] | 1 | True | 0.32 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458576dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1800s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.11 Core Time (ms) : 24.19 TIDL Subgraphs Processing Time (ms) : 24.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1280] | 1 | True | 0.44 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd7a1d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1432s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1434s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513113e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.48 Core Time (ms) : 40.21 TIDL Subgraphs Processing Time (ms) : 40.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50492469 bytes MEM: Free's : 26 free's of 50492469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_547] | 0 | - | 0.15 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5675299c73a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_30] | 1 | True | 0.23 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492690f40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.64 Core Time (ms) : 3.59 TIDL Subgraphs Processing Time (ms) : 3.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_184] | 0 | - | 0.41 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ff2de0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.50 Core Time (ms) : 8.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1691] | 0 | - | 11.53 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba103eba0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 241.98 Core Time (ms) : 241.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_356] | 0 | - | 0.90 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2030580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 28.10 Core Time (ms) : 28.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1389] | 0 | - | 0.19 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab84cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 31.74 Core Time (ms) : 31.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_803] | 0 | - | 1.80 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1f0970 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 808.96 Core Time (ms) : 808.96 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1423] | 0 | - | 0.15 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb2137560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.44 Core Time (ms) : 14.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1386] | 0 | - | 0.32 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c83280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.42 Core Time (ms) : 2.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1500] | 0 | - | 0.27 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a06a090 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.72 Core Time (ms) : 1.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_734] | 1 | True | 3.85 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ab3d10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.151s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1826s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1830s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001392103241601961 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 422.63 Core Time (ms) : 349.23 TIDL Subgraphs Processing Time (ms) : 347.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 545339261 bytes MEM: Free's : 26 free's of 545339261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1261] | 0 | - | 0.13 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354925a45c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.68 Core Time (ms) : 0.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1835] | 0 | - | 0.22 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20b6ca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.98 Core Time (ms) : 0.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1093] | 0 | - | 0.22 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467cccc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.01 Core Time (ms) : 1.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_601] | 1 | True | 0.49 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac6f3c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.180s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9113s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.01 Core Time (ms) : 12.14 TIDL Subgraphs Processing Time (ms) : 12.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1033] | 0 | - | 0.21 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45848f4a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.58 Core Time (ms) : 3.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_573] | 1 | True | 0.32 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516db5870 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.144s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2844s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.37 Core Time (ms) : 9.62 TIDL Subgraphs Processing Time (ms) : 9.50 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_253] | 0 | - | 6.12 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549268fae0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 125.71 Core Time (ms) : 125.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1757] | 0 | - | 0.29 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a06aff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_618] | 0 | - | 0.21 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c81f00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.00 Core Time (ms) : 1.00 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_771] | 0 | - | 0.37 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd7bf20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.62 Core Time (ms) : 1.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_222] | 1 | True | 0.30 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ff3b60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2433s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.74 Core Time (ms) : 3.21 TIDL Subgraphs Processing Time (ms) : 3.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1373] | 0 | - | 0.32 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20b6660 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.58 Core Time (ms) : 1.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1765] | 0 | - | 0.26 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad02db0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1486] | 0 | - | 1.05 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467cf280 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.27 Core Time (ms) : 10.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1599] | 0 | - | 0.27 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458579a90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.53 Core Time (ms) : 0.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_952] | 0 | - | 0.13 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dc1b70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_612] | 0 | - | 0.38 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c846d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 149.10 Core Time (ms) : 149.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_939] | 0 | - | 1.06 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a06b450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 214.51 Core Time (ms) : 214.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1526] | 0 | - | 0.20 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac17ce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.25 Core Time (ms) : 0.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_224] | 1 | True | 3.75 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ff5fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.146s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2490s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00030963001383282337 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 278.08 Core Time (ms) : 169.35 TIDL Subgraphs Processing Time (ms) : 167.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 539593317 bytes MEM: Free's : 26 free's of 539593317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_892] | 1 | True | 0.35 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac71f00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.154s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1982s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1986s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.20 Core Time (ms) : 13.54 TIDL Subgraphs Processing Time (ms) : 13.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1950] | 0 | - | 1.03 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45857ad60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.53 Core Time (ms) : 5.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1545] | 0 | - | 1.03 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516db85a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.47 Core Time (ms) : 16.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_28] | 1 | True | 0.21 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fcd850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.186s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5835s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.74 Core Time (ms) : 0.59 TIDL Subgraphs Processing Time (ms) : 0.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_46] | 0 | - | 2.73 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce66300 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 40.50 Core Time (ms) : 40.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1882] | 1 | True | 0.78 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad02560 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.190s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2198s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 50.70 Core Time (ms) : 37.75 TIDL Subgraphs Processing Time (ms) : 37.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1646] | 1 | True | 0.44 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc36ba10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.178s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8830s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.46 Core Time (ms) : 13.70 TIDL Subgraphs Processing Time (ms) : 13.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_29] | 0 | - | 5.41 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2030ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 45.08 Core Time (ms) : 45.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_285] | 0 | - | 0.67 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20b9cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.49 Core Time (ms) : 8.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_330] | 0 | - | 0.70 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c84920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.45 Core Time (ms) : 12.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_389] | 0 | - | 0.50 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac73770 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.88 Core Time (ms) : 4.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1739] | 0 | - | 2.13 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc36e630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 59.03 Core Time (ms) : 59.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1392] | 0 | - | 0.24 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f903650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.65 Core Time (ms) : 1.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_947] | 0 | - | 0.24 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466e5d00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.92 Core Time (ms) : 0.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_632] | 0 | - | 0.23 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac74720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.35 Core Time (ms) : 1.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1768] | 0 | - | 0.40 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9ed110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.12 Core Time (ms) : 3.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_393] | 1 | True | 2.47 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20b9e80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.179s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9774s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9786s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006023491290637722 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 290.42 Core Time (ms) : 171.60 TIDL Subgraphs Processing Time (ms) : 170.71 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 300712293 bytes MEM: Free's : 26 free's of 300712293 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1908] | 0 | - | 0.60 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad04ae0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.90 Core Time (ms) : 3.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_655] | 0 | - | 1.29 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c84e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.06 Core Time (ms) : 18.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1664] | 0 | - | 0.42 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f831d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.05 Core Time (ms) : 1.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_955] | 0 | - | 0.25 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466e63d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.85 Core Time (ms) : 0.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1245] | 1 | True | 0.30 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45857be90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.20 Core Time (ms) : 3.57 TIDL Subgraphs Processing Time (ms) : 3.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1605] | 0 | - | 0.27 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516db8a50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.77 Core Time (ms) : 0.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1980] | 0 | - | 0.39 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac75b70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.68 Core Time (ms) : 2.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_635] | 1 | True | 0.28 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b107730 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.112s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.64 Core Time (ms) : 3.53 TIDL Subgraphs Processing Time (ms) : 3.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_377] | 0 | - | 1.08 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa516870 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 147.39 Core Time (ms) : 147.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_15] | 1 | True | 0.77 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467cfcf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.139s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1836s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 68.52 Core Time (ms) : 57.81 TIDL Subgraphs Processing Time (ms) : 57.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1573] | 0 | - | 1.26 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9eea60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.70 Core Time (ms) : 8.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_4] | 0 | - | 0.29 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dbff20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_718] | 0 | - | 0.29 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45857ee40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1190] | 1 | True | 1.01 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1f3c00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.249s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012952647395713226 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 55.22 Core Time (ms) : 40.97 TIDL Subgraphs Processing Time (ms) : 40.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89076149 bytes MEM: Free's : 26 free's of 89076149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1068] | 0 | - | 0.18 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a06ca00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.70 Core Time (ms) : 0.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_824] | 0 | - | 0.43 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab8bcd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.61 Core Time (ms) : 10.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_946] | 0 | - | 0.25 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac1b2f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.17 Core Time (ms) : 0.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_818] | 1 | True | 0.38 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a06cca0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.223s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6544s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.80 Core Time (ms) : 9.01 TIDL Subgraphs Processing Time (ms) : 8.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1645] | 0 | - | 1.47 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dbb240 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 777.73 Core Time (ms) : 777.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1431] | 1 | True | 0.28 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458585660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.145s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2735s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2738s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.63 Core Time (ms) : 5.57 TIDL Subgraphs Processing Time (ms) : 5.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1030] | 0 | - | 0.24 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3990fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_497] | 0 | - | 1.27 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad058f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.01 Core Time (ms) : 6.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1363] | 0 | - | 1.22 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a398cd20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 27.84 Core Time (ms) : 27.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_357] | 0 | - | 0.26 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab8c2a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1084] | 1 | True | 0.51 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585812f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.22 Core Time (ms) : 17.34 TIDL Subgraphs Processing Time (ms) : 17.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_426] | 0 | - | 0.40 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a070090 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.72 Core Time (ms) : 2.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_809] | 0 | - | 0.15 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d6110 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1103] | 0 | - | 0.32 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac776b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.19 Core Time (ms) : 8.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1702] | 0 | - | 0.55 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d22b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.02 Core Time (ms) : 15.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1883] | 1 | True | 0.26 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa5160b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.120s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1437s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.47 Core Time (ms) : 2.97 TIDL Subgraphs Processing Time (ms) : 2.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_149] | 0 | - | 0.68 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687ea890 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 17.62 Core Time (ms) : 17.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_170] | 1 | True | 3.70 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c85bf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.161s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013933125081359568 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 302.82 Core Time (ms) : 251.31 TIDL Subgraphs Processing Time (ms) : 249.29 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 539593317 bytes MEM: Free's : 26 free's of 539593317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1962] | 0 | - | 0.30 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a070e10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.14 Core Time (ms) : 1.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1623] | 1 | True | 0.37 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1f4f20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.180s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.04 Core Time (ms) : 7.72 TIDL Subgraphs Processing Time (ms) : 7.59 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_36] | 0 | - | 0.46 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585851e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.12 Core Time (ms) : 1.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_524] | 0 | - | 0.23 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa42f530 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_236] | 0 | - | 0.80 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c12a40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.79 Core Time (ms) : 14.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1115] | 0 | - | 0.37 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac77df0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.59 Core Time (ms) : 3.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_893] | 0 | - | 0.69 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9eec30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.36 Core Time (ms) : 8.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1816] | 1 | True | 0.29 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a06fb70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.186s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.24 Core Time (ms) : 3.70 TIDL Subgraphs Processing Time (ms) : 3.52 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1284] | 0 | - | 0.20 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa5afa90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.52 Core Time (ms) : 0.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_903] | 0 | - | 0.16 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc37a390 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1345] | 0 | - | 2.39 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce67e30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.11 Core Time (ms) : 25.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1133] | 0 | - | 0.35 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d3940 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.36 Core Time (ms) : 5.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1795] | 0 | - | 0.32 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1f7d00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.48 Core Time (ms) : 4.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1108] | 0 | - | 2.64 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0986a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 53.73 Core Time (ms) : 53.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1409] | 0 | - | 4.63 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac78af0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.39 Core Time (ms) : 15.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_811] | 0 | - | 0.26 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc2852e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.19 Core Time (ms) : 1.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_794] | 1 | True | 0.40 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa51b3b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1393s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1395s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.37 Core Time (ms) : 12.54 TIDL Subgraphs Processing Time (ms) : 12.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1587] | 0 | - | 2.43 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458584c30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.25 Core Time (ms) : 14.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_47] | 1 | True | 0.43 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687ebd00 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.150s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1515s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.48 Core Time (ms) : 15.32 TIDL Subgraphs Processing Time (ms) : 15.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1046] | 1 | True | 1.53 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0738c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.159s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05238592554211476 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 77.74 Core Time (ms) : 63.65 TIDL Subgraphs Processing Time (ms) : 63.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 154950101 bytes MEM: Free's : 26 free's of 154950101 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_13] | 0 | - | 0.39 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad061c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.59 Core Time (ms) : 0.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1194] | 0 | - | 1.68 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dbc000 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.46 Core Time (ms) : 25.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_548] | 0 | - | 1.59 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1f8030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 32.26 Core Time (ms) : 32.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_622] | 0 | - | 0.20 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466ea770 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.36 Core Time (ms) : 0.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1251] | 1 | True | 0.60 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a398d850 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.80s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1690s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1693s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 36.78 Core Time (ms) : 34.24 TIDL Subgraphs Processing Time (ms) : 34.15 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1252] | 0 | - | 0.41 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc3716a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.01 Core Time (ms) : 1.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1782] | 1 | True | 0.49 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ab5710 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1886s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.05265966571547102 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.65 Core Time (ms) : 14.99 TIDL Subgraphs Processing Time (ms) : 14.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31820165 bytes MEM: Free's : 26 free's of 31820165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1231] | 0 | - | 0.23 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b29720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_498] | 0 | - | 0.39 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9ef670 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.35 Core Time (ms) : 1.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1005] | 0 | - | 6.14 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d4f00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.45 Core Time (ms) : 12.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_335] | 0 | - | 1.00 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa51d190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 141.84 Core Time (ms) : 141.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1166] | 1 | True | 0.41 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687ed340 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.139s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2291s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2294s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.19 Core Time (ms) : 7.32 TIDL Subgraphs Processing Time (ms) : 7.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_215] | 0 | - | 7.27 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20bc8b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 111.33 Core Time (ms) : 111.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_594] | 0 | - | 0.88 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad067e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.75 Core Time (ms) : 4.75 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1152] | 0 | - | 0.43 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c15380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.04 Core Time (ms) : 1.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_747] | 1 | True | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc3711c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.19 Core Time (ms) : 2.72 TIDL Subgraphs Processing Time (ms) : 2.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1769] | 0 | - | 1.22 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9f01a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.26 Core Time (ms) : 13.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_367] | 1 | True | 1.20 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ab7630 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.181s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8835s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 125.33 Core Time (ms) : 103.23 TIDL Subgraphs Processing Time (ms) : 103.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1404] | 0 | - | 1.48 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ff7a60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 32.91 Core Time (ms) : 32.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1408] | 0 | - | 1.56 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a398fa60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 45.42 Core Time (ms) : 45.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1034] | 0 | - | 0.15 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687f9100 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1342] | 1 | True | 0.65 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc373480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.106s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1487s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.20 Core Time (ms) : 18.45 TIDL Subgraphs Processing Time (ms) : 18.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1056] | 1 | True | 0.53 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2df0b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.199s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2650s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.93 Core Time (ms) : 16.59 TIDL Subgraphs Processing Time (ms) : 16.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1872] | 0 | - | 0.56 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687f0230 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.68 Core Time (ms) : 6.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1953] | 0 | - | 0.96 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c15430 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.59 Core Time (ms) : 21.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1613] | 0 | - | 0.47 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa51cb20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 17.38 Core Time (ms) : 17.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_511] | 0 | - | 0.36 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1f68f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.89 Core Time (ms) : 0.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1639] | 0 | - | 0.93 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad07b90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.88 Core Time (ms) : 16.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1776] | 0 | - | 0.84 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc374000 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 50.59 Core Time (ms) : 50.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_249] | 0 | - | 0.48 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687f0d90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.84 Core Time (ms) : 6.84 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_788] | 0 | - | 0.65 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0747f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.27 Core Time (ms) : 11.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_861] | 0 | - | 0.61 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1f87d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.20 Core Time (ms) : 22.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1742] | 0 | - | 0.37 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2e0ec0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.24 Core Time (ms) : 1.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1751] | 0 | - | 0.29 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dba870 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.73 Core Time (ms) : 0.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1715] | 1 | True | 0.39 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa521590 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1715s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.25 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_399] | 0 | - | 0.25 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f909400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.58 Core Time (ms) : 0.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1969] | 0 | - | 2.04 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c155e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 47.12 Core Time (ms) : 47.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_956] | 1 | True | 0.25 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5675299cf390 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.98s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012875171407235148 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.08 Core Time (ms) : 16.51 TIDL Subgraphs Processing Time (ms) : 16.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18240813 bytes MEM: Free's : 26 free's of 18240813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1403] | 0 | - | 2.15 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687f1250 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 66.50 Core Time (ms) : 66.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_467] | 1 | True | 0.43 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dbdf90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1432s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1434s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.70 Core Time (ms) : 9.49 TIDL Subgraphs Processing Time (ms) : 9.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_708] | 0 | - | 0.18 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2e15d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.97 Core Time (ms) : 0.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1521] | 0 | - | 1.51 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce68450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 373.31 Core Time (ms) : 373.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_514] | 0 | - | 0.16 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9f7d00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_886] | 0 | - | 0.93 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529abc8d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.31 Core Time (ms) : 4.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1582] | 0 | - | 0.53 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a076450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.03 Core Time (ms) : 5.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_810] | 0 | - | 0.86 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ff7c60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.33 Core Time (ms) : 2.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1239] | 0 | - | 0.48 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa520d80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.86 Core Time (ms) : 3.86 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1476] | 1 | True | 0.21 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d1f8760 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1840s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.65 Core Time (ms) : 0.55 TIDL Subgraphs Processing Time (ms) : 0.47 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1695] | 0 | - | 0.30 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3b54bf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1865] | 1 | True | 0.21 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac1e8d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1353s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.54 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.40 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_637] | 0 | - | 0.21 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc28bbf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.33 Core Time (ms) : 11.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1699] | 0 | - | 0.36 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1f9420 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_70] | 0 | - | 0.98 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9f1da0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.39 Core Time (ms) : 15.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1057] | 0 | - | 2.44 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458584d00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 62.67 Core Time (ms) : 62.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_790] | 1 | True | 0.47 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a099cf0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1412s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1415s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.28 Core Time (ms) : 7.13 TIDL Subgraphs Processing Time (ms) : 7.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1651] | 1 | True | 0.23 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2e87b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.81 Core Time (ms) : 1.78 TIDL Subgraphs Processing Time (ms) : 1.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1301] | 0 | - | 0.40 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dbe040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.76 Core Time (ms) : 0.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1851] | 1 | True | 0.33 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc375f10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.89 Core Time (ms) : 2.51 TIDL Subgraphs Processing Time (ms) : 2.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1145] | 0 | - | 0.38 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad0a2a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.02 Core Time (ms) : 1.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_706] | 0 | - | 15.59 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2030b30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 83.95 Core Time (ms) : 83.95 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_176] | 0 | - | 7.22 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3991d60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 93.70 Core Time (ms) : 93.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_865] | 0 | - | 1.63 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1fabc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 183.47 Core Time (ms) : 183.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_592] | 1 | True | 0.63 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354925a7ae0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1638s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0029605766221378117 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 32.02 Core Time (ms) : 29.30 TIDL Subgraphs Processing Time (ms) : 29.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50492469 bytes MEM: Free's : 26 free's of 50492469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_92] | 0 | - | 0.67 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa520de0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.74 Core Time (ms) : 1.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_171] | 1 | True | 0.38 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a07b070 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.18 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.11 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1968] | 0 | - | 0.36 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2ed350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_679] | 1 | True | 0.32 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab57f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.06 Core Time (ms) : 2.64 TIDL Subgraphs Processing Time (ms) : 2.60 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1965] | 0 | - | 15.51 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc377150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 87.68 Core Time (ms) : 87.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1678] | 0 | - | 0.46 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ada0af0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_515] | 0 | - | 2.39 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dbf370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 24.62 Core Time (ms) : 24.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1531] | 0 | - | 0.72 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a09aec0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.37 Core Time (ms) : 4.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1529] | 1 | True | 0.52 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c88b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.83s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.38 Core Time (ms) : 10.02 TIDL Subgraphs Processing Time (ms) : 9.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1341] | 0 | - | 0.18 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812f0f6e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_175] | 0 | - | 0.36 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a078170 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1668] | 0 | - | 1.57 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529abbd50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.27 Core Time (ms) : 16.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_795] | 1 | True | 0.37 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2e7400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.45 Core Time (ms) : 3.06 TIDL Subgraphs Processing Time (ms) : 3.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_462] | 0 | - | 0.76 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab7c50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.99 Core Time (ms) : 11.99 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1729] | 0 | - | 0.71 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ff9f70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.61 Core Time (ms) : 9.61 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_457] | 1 | True | 0.40 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f909ec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.124s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2012s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00034847194658466763 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 6.74 Core Time (ms) : 6.31 TIDL Subgraphs Processing Time (ms) : 6.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 22128853 bytes MEM: Free's : 26 free's of 22128853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1426] | 0 | - | 0.34 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492692d40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_19] | 0 | - | 0.55 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa521970 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.80 Core Time (ms) : 1.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1785] | 0 | - | 0.91 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad0b130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.17 Core Time (ms) : 6.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_115] | 1 | True | 2.01 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c89a90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1393s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013918601890109722 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 117.48 Core Time (ms) : 96.05 TIDL Subgraphs Processing Time (ms) : 95.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 205588549 bytes MEM: Free's : 26 free's of 205588549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_500] | 1 | True | 0.25 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f8f960 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1577s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.00 Core Time (ms) : 0.83 TIDL Subgraphs Processing Time (ms) : 0.78 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 15050965 bytes MEM: Free's : 26 free's of 15050965 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_814] | 0 | - | 0.76 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2e97d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.53 Core Time (ms) : 2.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_100] | 0 | - | 3.39 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a09c860 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 818.29 Core Time (ms) : 818.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_917] | 1 | True | 0.44 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354925a9a80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.53 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1850] | 0 | - | 0.75 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce69130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.48 Core Time (ms) : 2.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1877] | 0 | - | 0.42 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9f4f50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1576] | 0 | - | 0.20 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f90f70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_210] | 1 | True | 3.13 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa521d90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.160s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060112036577703665 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 278.73 Core Time (ms) : 245.64 TIDL Subgraphs Processing Time (ms) : 243.85 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 356725613 bytes MEM: Free's : 26 free's of 356725613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_808] | 1 | True | 0.81 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a07bb20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.121s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1856s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1859s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 26.09 Core Time (ms) : 22.06 TIDL Subgraphs Processing Time (ms) : 21.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1278] | 0 | - | 0.56 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab8140 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.19 Core Time (ms) : 2.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1595] | 1 | True | 0.69 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c15c30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1390s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.59 Core Time (ms) : 28.64 TIDL Subgraphs Processing Time (ms) : 28.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1308] | 1 | True | 0.24 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ffa190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.37 Core Time (ms) : 2.90 TIDL Subgraphs Processing Time (ms) : 2.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_67] | 0 | - | 0.48 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492695ec0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.52 Core Time (ms) : 12.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_327] | 1 | True | 0.61 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9f5cb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.84s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1449s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.85 Core Time (ms) : 9.28 TIDL Subgraphs Processing Time (ms) : 9.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1360] | 1 | True | 0.38 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687080f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2091s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2093s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.24 Core Time (ms) : 1.08 TIDL Subgraphs Processing Time (ms) : 1.02 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1907] | 0 | - | 1.24 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ffc1d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 329.73 Core Time (ms) : 329.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1464] | 0 | - | 0.27 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2e8fc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_124] | 0 | - | 0.34 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad10410 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_948] | 0 | - | 0.27 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1fac70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.63 Core Time (ms) : 0.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1421] | 0 | - | 0.22 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd81a90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.44 Core Time (ms) : 1.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1131] | 0 | - | 2.19 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab98d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 49.64 Core Time (ms) : 49.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1510] | 0 | - | 0.50 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac79080 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.07 Core Time (ms) : 2.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_411] | 1 | True | 0.30 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2006d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.74s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1321s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.46 Core Time (ms) : 0.40 TIDL Subgraphs Processing Time (ms) : 0.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1712] | 1 | True | 0.70 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687f41e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.129s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2007s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 31.79 Core Time (ms) : 27.00 TIDL Subgraphs Processing Time (ms) : 26.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1549] | 0 | - | 0.31 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b113220 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_943] | 0 | - | 0.76 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492696f30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.98 Core Time (ms) : 11.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1895] | 0 | - | 1.69 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad0c4b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 572.26 Core Time (ms) : 572.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1838] | 0 | - | 0.77 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce6bf80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.72 Core Time (ms) : 2.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1607] | 0 | - | 0.31 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c182d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.19 Core Time (ms) : 1.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_868] | 1 | True | 0.34 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5675299d4be0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1429s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.94 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1198] | 0 | - | 0.28 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f940e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_763] | 0 | - | 7.76 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9f70b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 124.10 Core Time (ms) : 124.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1700] | 0 | - | 0.35 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585855a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.29 Core Time (ms) : 1.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1469] | 0 | - | 1.37 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2ece00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.59 Core Time (ms) : 3.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_576] | 0 | - | 0.39 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1fbf40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.10 Core Time (ms) : 1.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1916] | 0 | - | 0.40 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c18ad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.64 Core Time (ms) : 0.64 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1746] | 0 | - | 0.65 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac10b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.19 Core Time (ms) : 1.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_640] | 1 | True | 0.34 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f941e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.140s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1561s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.67 Core Time (ms) : 1.44 TIDL Subgraphs Processing Time (ms) : 1.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1211] | 0 | - | 0.28 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecad0f1d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.58 Core Time (ms) : 0.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1189] | 0 | - | 0.32 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458586740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.24 Core Time (ms) : 1.24 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1101] | 0 | - | 3.52 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687f7bf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 46.55 Core Time (ms) : 46.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1648] | 0 | - | 0.51 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1fcaf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.78 Core Time (ms) : 5.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1394] | 0 | - | 0.23 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab90e90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_206] | 0 | - | 0.36 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dbf5c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_7] | 0 | - | 0.64 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492697c70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.69 Core Time (ms) : 1.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1293] | 0 | - | 0.41 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c195e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 31.71 Core Time (ms) : 31.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1572] | 0 | - | 0.43 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f97b30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.36 Core Time (ms) : 1.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1541] | 0 | - | 0.20 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcf027e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.37 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_301] | 1 | True | 0.64 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812ffe660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.153s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2264s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.77 Core Time (ms) : 17.52 TIDL Subgraphs Processing Time (ms) : 17.37 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_501] | 0 | - | 0.33 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45858c930 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1694] | 1 | True | 0.65 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c8c110 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1471s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1474s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 27.64 Core Time (ms) : 21.05 TIDL Subgraphs Processing Time (ms) : 20.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65231749 bytes MEM: Free's : 26 free's of 65231749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_209] | 0 | - | 0.25 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac7ea00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1693] | 1 | True | 0.24 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd81dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1693s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1696s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.59 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.46 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_551] | 0 | - | 0.64 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac2430 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.70 Core Time (ms) : 5.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_588] | 0 | - | 0.21 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cd6fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_860] | 0 | - | 0.26 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c1a630 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1078] | 0 | - | 1.22 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a081030 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 44.02 Core Time (ms) : 44.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_765] | 0 | - | 1.61 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458588680 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.88 Core Time (ms) : 18.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1773] | 0 | - | 1.16 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac7b910 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 35.34 Core Time (ms) : 35.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_273] | 0 | - | 0.48 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1fdc70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.25 Core Time (ms) : 9.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_471] | 0 | - | 0.19 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd84d00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_25] | 1 | True | 0.47 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dc1530 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2657s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2660s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.00 Core Time (ms) : 12.34 TIDL Subgraphs Processing Time (ms) : 12.20 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_967] | 0 | - | 8.20 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492698fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 101.72 Core Time (ms) : 101.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1614] | 0 | - | 0.92 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c1a9b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.47 Core Time (ms) : 20.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1905] | 0 | - | 1.29 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce6f2d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.32 Core Time (ms) : 18.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1796] | 0 | - | 14.55 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812fff940 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 57.60 Core Time (ms) : 57.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1517] | 0 | - | 0.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7d23350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_476] | 0 | - | 0.25 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2053e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.20 Core Time (ms) : 0.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_812] | 1 | True | 0.62 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b1fdc70 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1669s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001291071653989963 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 43.89 Core Time (ms) : 40.95 TIDL Subgraphs Processing Time (ms) : 40.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 31820165 bytes MEM: Free's : 26 free's of 31820165 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_218] | 1 | True | 1.05 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac1bd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.126s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545884 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 47.53 Core Time (ms) : 35.55 TIDL Subgraphs Processing Time (ms) : 35.45 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 89076149 bytes MEM: Free's : 26 free's of 89076149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_773] | 0 | - | 0.55 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad0c870 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.58 Core Time (ms) : 2.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_374] | 1 | True | 0.72 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dc39e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1456s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 29.43 Core Time (ms) : 20.13 TIDL Subgraphs Processing Time (ms) : 19.94 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_856] | 1 | True | 0.47 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c8f600 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 16.57 Core Time (ms) : 15.02 TIDL Subgraphs Processing Time (ms) : 14.95 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1999] | 0 | - | 0.50 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d5740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.91 Core Time (ms) : 1.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_572] | 0 | - | 3.73 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2f0320 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 66.29 Core Time (ms) : 66.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1506] | 1 | True | 0.79 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ab9a50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.13 Core Time (ms) : 29.34 TIDL Subgraphs Processing Time (ms) : 29.25 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1841] | 0 | - | 0.62 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c911f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.59 Core Time (ms) : 2.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1709] | 0 | - | 0.29 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad0d760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.41 Core Time (ms) : 1.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1179] | 0 | - | 0.25 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b118a40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1055] | 0 | - | 0.18 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d6430 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.62 Core Time (ms) : 0.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1216] | 1 | True | 0.47 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac7c3d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.99 Core Time (ms) : 16.92 TIDL Subgraphs Processing Time (ms) : 16.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_992] | 0 | - | 0.37 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c1be00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 42.01 Core Time (ms) : 42.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_560] | 0 | - | 0.45 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a081820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1257] | 0 | - | 0.16 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69fb39b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.11 Core Time (ms) : 0.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_342] | 0 | - | 0.70 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa523ec0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.53 Core Time (ms) : 2.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1000] | 1 | True | 0.31 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dcf8a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.118s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1847s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1850s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.29 Core Time (ms) : 0.26 TIDL Subgraphs Processing Time (ms) : 0.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12478853 bytes MEM: Free's : 26 free's of 12478853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_382] | 1 | True | 0.50 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921466efc60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.125s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2113s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.44 Core Time (ms) : 0.37 TIDL Subgraphs Processing Time (ms) : 0.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12970373 bytes MEM: Free's : 26 free's of 12970373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_555] | 0 | - | 0.42 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ac25450 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.10 Core Time (ms) : 1.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_678] | 0 | - | 0.64 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b200e00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.11 Core Time (ms) : 7.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1151] | 1 | True | 0.50 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a09ddd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1661s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.33 Core Time (ms) : 8.87 TIDL Subgraphs Processing Time (ms) : 8.81 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_422] | 0 | - | 2.33 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c1c2b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.58 Core Time (ms) : 13.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_81] | 0 | - | 0.33 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce74a60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1571] | 0 | - | 1.97 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac3ce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.18 Core Time (ms) : 2.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_546] | 1 | True | 0.43 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cdd0e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1443s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1445s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.04 Core Time (ms) : 0.92 TIDL Subgraphs Processing Time (ms) : 0.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_14] | 0 | - | 0.42 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458588190 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.55 Core Time (ms) : 1.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_84] | 1 | True | 0.56 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac7ef30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5384s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.07 Core Time (ms) : 10.00 TIDL Subgraphs Processing Time (ms) : 9.90 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1720] | 0 | - | 1.81 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c91ef0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 16.33 Core Time (ms) : 16.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1043] | 1 | True | 0.71 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321abc6a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1317s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.26 Core Time (ms) : 9.42 TIDL Subgraphs Processing Time (ms) : 9.38 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1346] | 1 | True | 0.40 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f985a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1661s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.98 Core Time (ms) : 0.88 TIDL Subgraphs Processing Time (ms) : 0.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1542] | 1 | True | 0.42 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad19760 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1753s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1755s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012709324273911826 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.25 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.19 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12478853 bytes MEM: Free's : 26 free's of 12478853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1266] | 0 | - | 0.47 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20c7700 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1396] | 0 | - | 2.66 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d9620 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.91 Core Time (ms) : 9.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1597] | 1 | True | 1.12 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce71050 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.88s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210055 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.85 Core Time (ms) : 15.19 TIDL Subgraphs Processing Time (ms) : 15.03 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83724677 bytes MEM: Free's : 26 free's of 83724677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1022] | 0 | - | 2.66 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0a0580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.60 Core Time (ms) : 7.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1690] | 0 | - | 0.66 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa5259e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.85 Core Time (ms) : 0.85 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1644] | 0 | - | 0.77 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba103fab0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.90 Core Time (ms) : 1.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1391] | 0 | - | 0.36 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b2061e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1868] | 0 | - | 1.27 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dc9b50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.91 Core Time (ms) : 5.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1309] | 0 | - | 1.16 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4585898f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.28 Core Time (ms) : 2.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1398] | 1 | True | 1.06 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0845c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1396s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1398s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.14 Core Time (ms) : 7.10 TIDL Subgraphs Processing Time (ms) : 7.04 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_436] | 0 | - | 0.26 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab99540 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.56 Core Time (ms) : 2.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_976] | 0 | - | 1.68 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad11ab0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.76 Core Time (ms) : 14.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_102] | 1 | True | 0.43 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20c1bd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1466s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1468s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.21 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.13 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1994] | 0 | - | 0.34 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321abe2b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.52 Core Time (ms) : 0.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1555] | 0 | - | 0.61 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b202d00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.63 Core Time (ms) : 5.63 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_722] | 1 | True | 0.78 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac81420 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1849s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1851s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.44 Core Time (ms) : 8.85 TIDL Subgraphs Processing Time (ms) : 8.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_201] | 1 | True | 9.34 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa525e90 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.78s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1407s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.006024973541706476 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 669.45 Core Time (ms) : 546.98 TIDL Subgraphs Processing Time (ms) : 544.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1108566893 bytes MEM: Free's : 26 free's of 1108566893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1054] | 0 | - | 2.30 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba103fb10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 52.17 Core Time (ms) : 52.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_582] | 0 | - | 0.95 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20c13d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.98 Core Time (ms) : 5.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1335] | 0 | - | 0.85 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321abec40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.30 Core Time (ms) : 1.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_387] | 0 | - | 1.00 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687f6e20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.11 Core Time (ms) : 8.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_791] | 0 | - | 0.24 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce767a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1383] | 0 | - | 0.92 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b203270 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.72 Core Time (ms) : 6.72 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1790] | 0 | - | 0.34 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49f9c310 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1069] | 0 | - | 0.44 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458591520 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1303] | 1 | True | 0.64 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce74890 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.135s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2179s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2181s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.92 Core Time (ms) : 9.11 TIDL Subgraphs Processing Time (ms) : 9.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_858] | 0 | - | 0.61 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab98ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1593] | 1 | True | 4.34 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dca610 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0983698814093516 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 397.28 Core Time (ms) : 362.10 TIDL Subgraphs Processing Time (ms) : 360.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 539593317 bytes MEM: Free's : 26 free's of 539593317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_317] | 1 | True | 0.43 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c969f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.136s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.25 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.16 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1180] | 0 | - | 1.48 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a087a20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 18.58 Core Time (ms) : 18.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_396] | 0 | - | 1.39 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac4750 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.78 Core Time (ms) : 2.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1290] | 0 | - | 0.45 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219d6f60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_479] | 0 | - | 0.27 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45858a350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.52 Core Time (ms) : 0.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1120] | 0 | - | 0.27 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fd63c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.29 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_18] | 0 | - | 0.41 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecab9a970 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1053] | 1 | True | 0.80 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c1c580 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.85s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1552s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.80 Core Time (ms) : 10.20 TIDL Subgraphs Processing Time (ms) : 10.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1567] | 0 | - | 0.89 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad11980 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.77 Core Time (ms) : 3.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1774] | 0 | - | 0.48 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd8b900 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_294] | 0 | - | 0.70 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c93760 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.41 Core Time (ms) : 1.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_799] | 0 | - | 0.53 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584a1120 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.08 Core Time (ms) : 0.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_125] | 0 | - | 0.84 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b204310 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.55 Core Time (ms) : 12.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_539] | 1 | True | 0.71 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486870e0c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.111s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.72 Core Time (ms) : 2.30 TIDL Subgraphs Processing Time (ms) : 2.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18240813 bytes MEM: Free's : 26 free's of 18240813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_259] | 1 | True | 2.16 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20c0480 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.86s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5450s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013933627009714482 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 164.17 Core Time (ms) : 146.12 TIDL Subgraphs Processing Time (ms) : 145.54 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 253917013 bytes MEM: Free's : 26 free's of 253917013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1912] | 1 | True | 0.55 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3992810 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1546s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.16 Core Time (ms) : 6.39 TIDL Subgraphs Processing Time (ms) : 6.31 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1618] | 0 | - | 0.64 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ac09c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.00 Core Time (ms) : 5.00 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1316] | 0 | - | 0.44 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac841c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.97 Core Time (ms) : 3.97 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_550] | 0 | - | 1.09 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2f03c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.41 Core Time (ms) : 8.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_5] | 0 | - | 0.40 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd8bce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1221] | 0 | - | 0.46 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45858b5a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.53 Core Time (ms) : 0.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_234] | 0 | - | 0.37 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d8850 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.66 Core Time (ms) : 0.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1750] | 0 | - | 0.99 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39941e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.90 Core Time (ms) : 2.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_216] | 1 | True | 0.40 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69fb6b30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.101s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1752s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.55 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.42 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1465] | 1 | True | 0.82 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c95060 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.161s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013912426325924823 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.88 Core Time (ms) : 48.33 TIDL Subgraphs Processing Time (ms) : 48.12 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 83724677 bytes MEM: Free's : 26 free's of 83724677 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1306] | 1 | True | 0.49 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687fb240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 7.51 Core Time (ms) : 6.60 TIDL Subgraphs Processing Time (ms) : 6.56 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1556] | 0 | - | 0.52 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c206e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.05 Core Time (ms) : 2.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1259] | 1 | True | 0.69 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219d7080 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1655s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0029605766221378117 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 30.14 Core Time (ms) : 26.92 TIDL Subgraphs Processing Time (ms) : 26.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 50492469 bytes MEM: Free's : 26 free's of 50492469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_148] | 1 | True | 0.89 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac85060 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.82s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.96 Core Time (ms) : 21.39 TIDL Subgraphs Processing Time (ms) : 21.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1734] | 0 | - | 0.52 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b11c590 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.10 Core Time (ms) : 0.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_698] | 0 | - | 0.41 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce80e40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_108] | 0 | - | 0.60 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad12a70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.19 Core Time (ms) : 3.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1884] | 0 | - | 0.91 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d94c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.70 Core Time (ms) : 4.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1833] | 0 | - | 1.20 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45858d810 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.98 Core Time (ms) : 8.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_180] | 0 | - | 0.45 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529acb7f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_179] | 1 | True | 0.79 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0a1910 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.154s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 18.28 Core Time (ms) : 16.04 TIDL Subgraphs Processing Time (ms) : 15.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_152] | 1 | True | 0.61 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a089100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1822s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1825s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.29 Core Time (ms) : 10.58 TIDL Subgraphs Processing Time (ms) : 10.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1856] | 1 | True | 0.80 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10404b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1471s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 41.57 Core Time (ms) : 38.39 TIDL Subgraphs Processing Time (ms) : 38.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_829] | 0 | - | 0.52 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687fd400 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.80 Core Time (ms) : 5.80 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1797] | 0 | - | 0.61 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce77d10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.25 Core Time (ms) : 1.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1993] | 0 | - | 0.60 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c1f200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 79.86 Core Time (ms) : 79.86 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_140] | 0 | - | 0.38 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b204c10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.79 Core Time (ms) : 0.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1714] | 0 | - | 1.69 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac5b70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 32.37 Core Time (ms) : 32.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_603] | 0 | - | 1.72 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ac2670 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 76.68 Core Time (ms) : 76.68 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_732] | 0 | - | 1.69 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad12a00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 26.41 Core Time (ms) : 26.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1397] | 0 | - | 2.45 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c97430 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 29.28 Core Time (ms) : 29.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_929] | 0 | - | 1.61 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2f10f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.20 Core Time (ms) : 23.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_310] | 0 | - | 0.43 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a38aa770 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.18 Core Time (ms) : 0.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1636] | 0 | - | 0.28 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a08a430 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.55 Core Time (ms) : 0.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_854] | 0 | - | 0.39 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac8dfb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_376] | 0 | - | 0.80 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687fd810 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.50 Core Time (ms) : 10.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1412] | 1 | True | 1.23 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b205a20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.94 Core Time (ms) : 21.26 TIDL Subgraphs Processing Time (ms) : 21.21 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_217] | 0 | - | 0.21 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0ad2d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_305] | 1 | True | 5.23 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467d9ec0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1542s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1546s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013933125081359568 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 300.78 Core Time (ms) : 252.67 TIDL Subgraphs Processing Time (ms) : 251.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 539593317 bytes MEM: Free's : 26 free's of 539593317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_105] | 0 | - | 0.15 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b383a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_801] | 1 | True | 0.70 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce784e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1543s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1545s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 17.04 Core Time (ms) : 15.25 TIDL Subgraphs Processing Time (ms) : 15.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_985] | 0 | - | 0.63 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10438d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.62 Core Time (ms) : 3.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_441] | 1 | True | 0.54 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba49fa3230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1277s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0013882237876142317 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.83 Core Time (ms) : 8.39 TIDL Subgraphs Processing Time (ms) : 8.34 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33908013 bytes MEM: Free's : 26 free's of 33908013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_151] | 0 | - | 7.61 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0a5100 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 75.05 Core Time (ms) : 75.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1376] | 1 | True | 0.95 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a39964c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012946247845935534 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 48.54 Core Time (ms) : 42.73 TIDL Subgraphs Processing Time (ms) : 42.64 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76366549 bytes MEM: Free's : 26 free's of 76366549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1707] | 0 | - | 1.20 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c20b60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.19 Core Time (ms) : 10.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1310] | 0 | - | 0.91 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac873a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.48 Core Time (ms) : 2.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1890] | 0 | - | 2.12 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45858df60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 403.99 Core Time (ms) : 403.99 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_621] | 0 | - | 0.36 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fd8e70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1947] | 1 | True | 2.94 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a08e810 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1424s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00030966523616425247 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 121.43 Core Time (ms) : 98.09 TIDL Subgraphs Processing Time (ms) : 96.62 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 356725613 bytes MEM: Free's : 26 free's of 356725613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_786] | 0 | - | 0.48 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba1042cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.98 Core Time (ms) : 0.98 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_813] | 0 | - | 0.71 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687febb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 182.11 Core Time (ms) : 182.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_867] | 0 | - | 0.50 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fd9370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 116.48 Core Time (ms) : 116.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_987] | 0 | - | 0.34 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce7ea50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.02 Core Time (ms) : 0.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1584] | 0 | - | 0.95 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9f8360 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 149.36 Core Time (ms) : 149.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1911] | 0 | - | 0.24 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd8f830 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1606] | 0 | - | 0.21 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b120990 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1966] | 0 | - | 0.17 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3a2d040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.33 Core Time (ms) : 0.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1492] | 0 | - | 14.47 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10446f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 59.58 Core Time (ms) : 59.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1886] | 0 | - | 0.33 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac882e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 22.47 Core Time (ms) : 22.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1788] | 0 | - | 1.01 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20c3800 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.35 Core Time (ms) : 3.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1859] | 0 | - | 0.60 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac6740 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.28 Core Time (ms) : 2.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1493] | 1 | True | 0.57 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2f1c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.52 Core Time (ms) : 9.89 TIDL Subgraphs Processing Time (ms) : 9.82 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_20] | 0 | - | 14.46 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad14550 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 174.17 Core Time (ms) : 174.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1679] | 1 | True | 6.81 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3997cd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.157s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2460s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2463s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060195041117528025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 533.27 Core Time (ms) : 463.66 TIDL Subgraphs Processing Time (ms) : 459.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 778891509 bytes MEM: Free's : 26 free's of 778891509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1105] | 1 | True | 0.89 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ac3c40 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1360s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 22.66 Core Time (ms) : 19.05 TIDL Subgraphs Processing Time (ms) : 18.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_159] | 0 | - | 1.33 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce7bb70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.00 Core Time (ms) : 3.00 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1744] | 0 | - | 3.23 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b209f60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.91 Core Time (ms) : 4.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1634] | 0 | - | 0.60 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c21e20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.18 Core Time (ms) : 5.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_258] | 0 | - | 0.41 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848687ff750 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.13 Core Time (ms) : 1.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_506] | 0 | - | 0.44 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac88b20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.28 Core Time (ms) : 1.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_144] | 0 | - | 0.24 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868806070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_738] | 0 | - | 0.71 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9f8780 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.94 Core Time (ms) : 2.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1814] | 0 | - | 0.32 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516ce3ca0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.14 Core Time (ms) : 1.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1631] | 1 | True | 0.62 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2f4c50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1566s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.27 Core Time (ms) : 8.76 TIDL Subgraphs Processing Time (ms) : 8.69 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1960] | 0 | - | 0.33 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5675299ddc60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_870] | 1 | True | 0.67 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac8a0d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1356s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.04 Core Time (ms) : 9.44 TIDL Subgraphs Processing Time (ms) : 9.39 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1219] | 0 | - | 0.81 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c231d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.49 Core Time (ms) : 2.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1733] | 0 | - | 2.75 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5848688003e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 60.37 Core Time (ms) : 60.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_394] | 1 | True | 1.01 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7bae960 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.005981567699147196 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 56.22 Core Time (ms) : 50.88 TIDL Subgraphs Processing Time (ms) : 50.74 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 96616845 bytes MEM: Free's : 26 free's of 96616845 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1268] | 0 | - | 0.30 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516ce2f10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.14 Core Time (ms) : 0.14 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1873] | 0 | - | 0.27 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219dc2a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.30 Core Time (ms) : 0.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1106] | 1 | True | 0.42 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fd9830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.90s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1425s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.01 Core Time (ms) : 0.88 TIDL Subgraphs Processing Time (ms) : 0.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_575] | 0 | - | 0.78 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac8930 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.87 Core Time (ms) : 1.87 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1941] | 0 | - | 0.75 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45858ec50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.37 Core Time (ms) : 2.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1258] | 1 | True | 0.51 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d20acd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.77s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.94 Core Time (ms) : 0.82 TIDL Subgraphs Processing Time (ms) : 0.79 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1076] | 0 | - | 0.72 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dce040 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.76 Core Time (ms) : 5.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_986] | 1 | True | 0.27 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ac6c20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.92s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1356s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.19 Core Time (ms) : 2.79 TIDL Subgraphs Processing Time (ms) : 2.75 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_849] | 1 | True | 0.62 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9f8d20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.42 Core Time (ms) : 18.33 TIDL Subgraphs Processing Time (ms) : 18.27 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_246] | 1 | True | 0.89 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x635492698fa0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.164s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.38 Core Time (ms) : 30.17 TIDL Subgraphs Processing Time (ms) : 30.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_664] | 1 | True | 0.59 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac8b1a0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 20.52 Core Time (ms) : 18.91 TIDL Subgraphs Processing Time (ms) : 18.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_887] | 0 | - | 2.34 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20c6b90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 31.22 Core Time (ms) : 31.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1020] | 0 | - | 0.29 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce81bd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_859] | 0 | - | 0.89 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ac8870 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.26 Core Time (ms) : 1.26 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_726] | 0 | - | 0.43 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c237b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.07 Core Time (ms) : 1.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_296] | 1 | True | 0.42 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce7c230 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.38 Core Time (ms) : 4.79 TIDL Subgraphs Processing Time (ms) : 4.73 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1027] | 0 | - | 0.25 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d20efe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.30 Core Time (ms) : 0.30 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_838] | 0 | - | 13.54 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac9da0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 162.47 Core Time (ms) : 162.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_680] | 0 | - | 0.59 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c9b420 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.36 Core Time (ms) : 1.36 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1630] | 1 | True | 0.75 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9fb8e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.105s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1733s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 24.18 Core Time (ms) : 18.71 TIDL Subgraphs Processing Time (ms) : 18.55 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1457] | 0 | - | 0.30 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac8d720 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.95 Core Time (ms) : 0.95 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_255] | 0 | - | 0.23 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584a4c40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1294] | 0 | - | 0.23 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd1f60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.03 Core Time (ms) : 0.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1300] | 0 | - | 0.78 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c24020 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.71 Core Time (ms) : 2.71 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_779] | 0 | - | 1.11 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2f97d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.18 Core Time (ms) : 2.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_767] | 0 | - | 4.10 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce7ef10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.16 Core Time (ms) : 15.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1119] | 1 | True | 0.45 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516ce53b0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.95s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1489s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.01 Core Time (ms) : 0.86 TIDL Subgraphs Processing Time (ms) : 0.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_400] | 0 | - | 0.49 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e45858fb40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.34 Core Time (ms) : 1.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_2000] | 0 | - | 1.64 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549269b1c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.22 Core Time (ms) : 6.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_638] | 0 | - | 0.87 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac8e070 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.06 Core Time (ms) : 2.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_240] | 0 | - | 5.89 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a08f680 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.25 Core Time (ms) : 23.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1035] | 0 | - | 0.39 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219df350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.22 Core Time (ms) : 0.22 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_165] | 1 | True | 0.89 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c99dd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.052506441567980795 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 50.82 Core Time (ms) : 39.52 TIDL Subgraphs Processing Time (ms) : 39.32 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65231749 bytes MEM: Free's : 26 free's of 65231749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1478] | 0 | - | 0.18 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd49d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.05 Core Time (ms) : 0.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_123] | 0 | - | 1.40 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9fc940 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 197.90 Core Time (ms) : 197.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1110] | 0 | - | 0.33 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584a6a10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.19 Core Time (ms) : 0.19 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_16] | 0 | - | 0.30 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b3a570 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.34 Core Time (ms) : 0.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_624] | 0 | - | 0.44 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321aca510 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.11 Core Time (ms) : 7.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_98] | 0 | - | 2.15 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd1170 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 44.89 Core Time (ms) : 44.89 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_430] | 0 | - | 0.40 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458591560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.83 Core Time (ms) : 1.83 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1921] | 0 | - | 1.27 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c252d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.35 Core Time (ms) : 5.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1104] | 0 | - | 0.39 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2105d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.27 Core Time (ms) : 2.27 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_704] | 1 | True | 0.56 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac8fc10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1418s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1421s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 19.38 Core Time (ms) : 15.58 TIDL Subgraphs Processing Time (ms) : 15.44 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1326] | 0 | - | 0.42 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219e0880 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.32 Core Time (ms) : 1.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_751] | 1 | True | 0.35 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b209190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.153s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2715s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2718s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 5.35 Core Time (ms) : 4.32 TIDL Subgraphs Processing Time (ms) : 4.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_419] | 0 | - | 0.27 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7bb2ea0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1748] | 0 | - | 0.37 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458593000 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.60 Core Time (ms) : 1.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1810] | 0 | - | 0.22 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d210dd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.41 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_388] | 0 | - | 0.30 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868717ad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.13 Core Time (ms) : 21.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1673] | 0 | - | 1.08 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c9e3b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.62 Core Time (ms) : 15.62 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1766] | 0 | - | 0.64 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321acbc10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.45 Core Time (ms) : 7.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_945] | 0 | - | 0.56 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b20b130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.09 Core Time (ms) : 3.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_417] | 0 | - | 1.08 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecaba6af0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.92 Core Time (ms) : 14.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1514] | 1 | True | 0.22 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20cba80 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.109s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.44 Core Time (ms) : 0.41 TIDL Subgraphs Processing Time (ms) : 0.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_308] | 0 | - | 1.04 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2fb950 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.42 Core Time (ms) : 2.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1260] | 0 | - | 0.48 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584a9aa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1858] | 1 | True | 0.58 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549269be50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.57 Core Time (ms) : 8.92 TIDL Subgraphs Processing Time (ms) : 8.84 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_38] | 0 | - | 0.74 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868801b80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.10 Core Time (ms) : 7.10 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1158] | 0 | - | 0.44 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20c8a90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1498] | 0 | - | 0.37 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467dc910 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.41 Core Time (ms) : 1.41 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1918] | 0 | - | 0.57 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9fd6e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.17 Core Time (ms) : 8.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1982] | 1 | True | 2.55 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b20beb0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.107s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1531s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00030966523616425247 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 116.27 Core Time (ms) : 91.40 TIDL Subgraphs Processing Time (ms) : 90.23 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 356725613 bytes MEM: Free's : 26 free's of 356725613 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1909] | 0 | - | 14.36 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e458593cc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3681.42 Core Time (ms) : 3681.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_876] | 0 | - | 0.74 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321acb920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 15.09 Core Time (ms) : 15.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1961] | 0 | - | 0.40 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467dda60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.08 Core Time (ms) : 2.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_106] | 1 | True | 0.51 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c26190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.134s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1670s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 15.87 Core Time (ms) : 12.65 TIDL Subgraphs Processing Time (ms) : 12.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1834] | 1 | True | 0.33 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fdf400 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.168s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3378s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.28 Core Time (ms) : 1.15 TIDL Subgraphs Processing Time (ms) : 1.06 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_667] | 1 | True | 0.89 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549269d840 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.155s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642532 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 52.43 Core Time (ms) : 36.09 TIDL Subgraphs Processing Time (ms) : 35.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 100503989 bytes MEM: Free's : 26 free's of 100503989 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1393] | 0 | - | 0.59 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868801ed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.28 Core Time (ms) : 10.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_266] | 0 | - | 0.35 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f914b40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.81 Core Time (ms) : 0.81 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_135] | 0 | - | 0.41 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c9dbf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.90 Core Time (ms) : 2.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_352] | 0 | - | 0.46 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fe19f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.88 Core Time (ms) : 7.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1554] | 0 | - | 0.57 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467de5c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.17 Core Time (ms) : 6.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_802] | 1 | True | 0.44 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac90c10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.114s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 8.60 Core Time (ms) : 7.96 TIDL Subgraphs Processing Time (ms) : 7.88 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1058] | 1 | True | 0.42 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d305460 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.130s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6111s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6116s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.32 Core Time (ms) : 0.29 TIDL Subgraphs Processing Time (ms) : 0.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12478853 bytes MEM: Free's : 26 free's of 12478853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1283] | 1 | True | 7.73 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa527ad0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.68s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1241s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1243s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545875 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 323.92 Core Time (ms) : 255.76 TIDL Subgraphs Processing Time (ms) : 253.36 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 1108566893 bytes MEM: Free's : 26 free's of 1108566893 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1721] | 0 | - | 0.38 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c2bdf0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_764] | 0 | - | 0.24 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cead70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_204] | 1 | True | 0.82 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f9feac0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1622s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1625s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003100000311834466 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 28.82 Core Time (ms) : 23.09 TIDL Subgraphs Processing Time (ms) : 22.96 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76366549 bytes MEM: Free's : 26 free's of 76366549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1528] | 0 | - | 0.31 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ad66b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_820] | 1 | True | 0.60 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7c9e240 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.103s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.06 Core Time (ms) : 11.89 TIDL Subgraphs Processing Time (ms) : 11.80 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_418] | 0 | - | 1.27 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20cc0b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.49 Core Time (ms) : 7.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1725] | 0 | - | 2.22 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2fd420 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 45.88 Core Time (ms) : 45.88 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1206] | 0 | - | 1.53 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868803b80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.39 Core Time (ms) : 12.39 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1732] | 0 | - | 0.36 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac93950 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.66 Core Time (ms) : 1.66 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1467] | 1 | True | 0.84 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd2970 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.127s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1452s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 25.09 Core Time (ms) : 19.71 TIDL Subgraphs Processing Time (ms) : 19.58 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1626] | 1 | True | 0.46 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c2c5d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.115s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2125s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2129s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.21 Core Time (ms) : 1.16 TIDL Subgraphs Processing Time (ms) : 1.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1784] | 0 | - | 1.35 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d20321f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 155.55 Core Time (ms) : 155.55 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1125] | 0 | - | 1.25 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467df2f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 9.92 Core Time (ms) : 9.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1181] | 1 | True | 0.46 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63549269ec50 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.154s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2561s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.45 Core Time (ms) : 3.37 TIDL Subgraphs Processing Time (ms) : 3.22 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_650] | 0 | - | 0.33 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219e3b00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.28 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1536] | 0 | - | 0.46 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc378a20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.65 Core Time (ms) : 1.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_800] | 0 | - | 0.18 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac9daa0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.13 Core Time (ms) : 0.13 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_933] | 0 | - | 0.45 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7bb5bd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.67 Core Time (ms) : 0.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1289] | 0 | - | 0.46 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321acde10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.59 Core Time (ms) : 3.59 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_611] | 1 | True | 0.49 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b41260 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.134s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2182s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 1.00 Core Time (ms) : 0.90 TIDL Subgraphs Processing Time (ms) : 0.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1924] | 1 | True | 0.96 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac94980 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.125s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 38.95 Core Time (ms) : 34.00 TIDL Subgraphs Processing Time (ms) : 33.89 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_696] | 0 | - | 0.80 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926a32a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.43 Core Time (ms) : 7.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_609] | 1 | True | 0.52 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f917030 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.152s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2671s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2674s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003095740677705007 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 2.01 Core Time (ms) : 1.75 TIDL Subgraphs Processing Time (ms) : 1.66 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 14236413 bytes MEM: Free's : 26 free's of 14236413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_970] | 0 | - | 0.72 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc378920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 6.91 Core Time (ms) : 6.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1015] | 0 | - | 1.36 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd4c00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.77 Core Time (ms) : 19.77 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_390] | 0 | - | 2.27 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7ca0e40 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 21.78 Core Time (ms) : 21.78 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1525] | 0 | - | 0.47 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ace480 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.16 Core Time (ms) : 1.16 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_360] | 0 | - | 1.00 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce7f920 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 11.42 Core Time (ms) : 11.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1353] | 0 | - | 2.45 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c2b5b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 44.07 Core Time (ms) : 44.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1985] | 1 | True | 0.39 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745fa070f0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.132s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2048s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2052s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.25 Core Time (ms) : 0.21 TIDL Subgraphs Processing Time (ms) : 0.14 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_904] | 0 | - | 0.66 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20cd470 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.43 Core Time (ms) : 3.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1378] | 0 | - | 0.58 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69fbd600 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 114.91 Core Time (ms) : 114.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1351] | 0 | - | 0.46 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467def90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.28 Core Time (ms) : 12.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_208] | 0 | - | 0.41 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354925b8be0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 20.03 Core Time (ms) : 20.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_507] | 0 | - | 0.39 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2031240 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.40 Core Time (ms) : 0.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_65] | 1 | True | 0.39 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc3790d0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.97s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096652361642535 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 4.34 Core Time (ms) : 3.75 TIDL Subgraphs Processing Time (ms) : 3.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19817213 bytes MEM: Free's : 26 free's of 19817213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1014] | 0 | - | 0.35 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219e4ff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.51 Core Time (ms) : 0.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1927] | 0 | - | 0.49 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac977a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.79 Core Time (ms) : 2.79 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_331] | 1 | True | 0.69 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868803f10 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.116s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1404s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 12.36 Core Time (ms) : 10.19 TIDL Subgraphs Processing Time (ms) : 10.08 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1754] | 0 | - | 0.62 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745fa04fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.49 Core Time (ms) : 5.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_2] | 0 | - | 9.46 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b20ee50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 49.73 Core Time (ms) : 49.73 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1128] | 0 | - | 0.62 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a399a370 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.17 Core Time (ms) : 5.17 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_283] | 1 | True | 0.23 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926a7ab0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.123s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1538s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.27 Core Time (ms) : 0.24 TIDL Subgraphs Processing Time (ms) : 0.17 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12305149 bytes MEM: Free's : 26 free's of 12305149 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_406] | 0 | - | 0.36 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219e6680 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.08 Core Time (ms) : 1.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_178] | 0 | - | 0.54 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2033ed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.70 Core Time (ms) : 4.70 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1448] | 0 | - | 0.89 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467e0390 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.82 Core Time (ms) : 1.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_264] | 0 | - | 0.69 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc37b650 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.05 Core Time (ms) : 4.05 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1336] | 1 | True | 0.47 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0a64e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.110s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.40 Core Time (ms) : 8.57 TIDL Subgraphs Processing Time (ms) : 8.51 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_737] | 0 | - | 0.31 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20cc700 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1755] | 0 | - | 1.59 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbce80480 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 23.67 Core Time (ms) : 23.67 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1318] | 0 | - | 1.31 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac96a70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.53 Core Time (ms) : 13.53 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1140] | 0 | - | 2.17 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926a5d30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.92 Core Time (ms) : 7.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_261] | 1 | True | 0.60 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745fa069e0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.94s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 14.27 Core Time (ms) : 12.39 TIDL Subgraphs Processing Time (ms) : 12.33 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_736] | 0 | - | 0.30 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c83219e87c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.09 Core Time (ms) : 0.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_494] | 0 | - | 0.86 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2fe9a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.91 Core Time (ms) : 2.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_320] | 0 | - | 0.49 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd4ce0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.11 Core Time (ms) : 5.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_268] | 0 | - | 0.38 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486871e0f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_519] | 0 | - | 2.06 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb20cf1b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 51.57 Core Time (ms) : 51.57 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_269] | 0 | - | 0.36 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a3999b80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.52 Core Time (ms) : 0.52 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_244] | 0 | - | 0.18 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69fbea50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.48 Core Time (ms) : 0.48 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1401] | 0 | - | 0.38 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f4ab60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.23 Core Time (ms) : 0.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1692] | 0 | - | 0.61 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ad2840 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.65 Core Time (ms) : 3.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1282] | 1 | True | 0.33 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812f16d30 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.96s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1431s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.51 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.41 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1547] | 0 | - | 0.76 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc37e4c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.82 Core Time (ms) : 1.82 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1395] | 0 | - | 1.02 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0a80a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 5.02 Core Time (ms) : 5.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1656] | 0 | - | 0.26 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868805930 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1160] | 0 | - | 0.61 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a399b910 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.18 Core Time (ms) : 12.18 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1628] | 0 | - | 0.61 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467e0eb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.92 Core Time (ms) : 1.92 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1696] | 0 | - | 0.43 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd4e90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.44 Core Time (ms) : 0.44 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1012] | 0 | - | 0.44 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d20345f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.91 Core Time (ms) : 1.91 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1743] | 0 | - | 0.60 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745fa07ed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.28 Core Time (ms) : 1.28 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_716] | 0 | - | 0.83 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628813002380 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.56 Core Time (ms) : 13.56 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_700] | 0 | - | 0.39 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x58486871dd80 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.02 Core Time (ms) : 1.02 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_48] | 0 | - | 0.72 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0908f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.90 Core Time (ms) : 14.90 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_825] | 0 | - | 1.16 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2ff1d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 19.49 Core Time (ms) : 19.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1672] | 1 | True | 0.36 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ad2490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.87s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003103445889883462 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 9.23 Core Time (ms) : 8.04 TIDL Subgraphs Processing Time (ms) : 7.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 30018269 bytes MEM: Free's : 26 free's of 30018269 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1011] | 0 | - | 0.25 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516cecf00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_496] | 0 | - | 0.22 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f4b800 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1413] | 0 | - | 0.89 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7ca1b30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 198.34 Core Time (ms) : 198.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1242] | 0 | - | 0.84 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a399c150 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.04 Core Time (ms) : 1.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1274] | 0 | - | 1.35 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868808580 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 25.49 Core Time (ms) : 25.49 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_757] | 0 | - | 0.19 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc295be0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.06 Core Time (ms) : 0.06 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_456] | 0 | - | 0.60 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467e3300 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.54 Core Time (ms) : 1.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_136] | 1 | True | 0.94 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac977c0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.128s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1913s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012946247845935534 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 62.37 Core Time (ms) : 56.84 TIDL Subgraphs Processing Time (ms) : 56.70 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76366549 bytes MEM: Free's : 26 free's of 76366549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1193] | 0 | - | 0.42 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745f91e6c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.40 Core Time (ms) : 0.40 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_662] | 0 | - | 0.23 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd6a00 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1657] | 0 | - | 0.25 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d1f4d1e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.58 Core Time (ms) : 0.58 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1731] | 0 | - | 0.75 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c2ce20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 4.11 Core Time (ms) : 4.11 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1143] | 0 | - | 0.95 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ad3d90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.96 Core Time (ms) : 1.96 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_372] | 0 | - | 0.23 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc37fbe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.31 Core Time (ms) : 0.31 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_529] | 0 | - | 0.42 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69fbf200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.45 Core Time (ms) : 0.45 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_428] | 0 | - | 0.48 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd96cc0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.32 Core Time (ms) : 2.32 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_900] | 0 | - | 0.21 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd9640 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.35 Core Time (ms) : 0.35 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1013] | 0 | - | 0.53 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2037500 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.54 Core Time (ms) : 2.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1090] | 0 | - | 1.22 | |
|
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5dba4a0915f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.42 Core Time (ms) : 13.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1073] | 0 | - | 0.28 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628813002cb0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.46 Core Time (ms) : 0.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_973] | 0 | - | 0.34 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc37fb20 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_745] | 0 | - | 0.39 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745fa08440 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 10.23 Core Time (ms) : 10.23 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_362] | 0 | - | 0.99 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd8d50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.96 Core Time (ms) : 8.96 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_922] | 0 | - | 1.18 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467e3800 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 14.01 Core Time (ms) : 14.01 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1809] | 0 | - | 0.58 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628813002fe0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.54 Core Time (ms) : 2.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_597] | 0 | - | 0.22 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69fc0770 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.12 Core Time (ms) : 0.12 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1723] | 1 | True | 0.65 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc381490 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.119s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.59 Core Time (ms) : 18.44 TIDL Subgraphs Processing Time (ms) : 18.35 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_626] | 0 | - | 0.42 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd988a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.74 Core Time (ms) : 0.74 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_318] | 0 | - | 0.61 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a399d2b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.69 Core Time (ms) : 0.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_699] | 0 | - | 1.44 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7ca4560 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 3.04 Core Time (ms) : 3.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1237] | 0 | - | 0.39 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745fa0a2d0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.43 Core Time (ms) : 0.43 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_309] | 0 | - | 0.20 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c358f0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_695] | 1 | True | 3.87 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d6a0ab660 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1564s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1567s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.001392103241601961 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 253.22 Core Time (ms) : 214.17 TIDL Subgraphs Processing Time (ms) : 212.86 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 545339261 bytes MEM: Free's : 26 free's of 545339261 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_51] | 0 | - | 0.49 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d20371e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.94 Core Time (ms) : 0.94 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1168] | 0 | - | 0.39 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926ab200 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_750] | 0 | - | 0.43 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d303350 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.04 Core Time (ms) : 0.04 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_968] | 0 | - | 0.62 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecac99f90 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.34 Core Time (ms) : 1.34 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_660] | 1 | True | 0.45 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fe8220 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.100s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1538s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003112851765991359 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.33 Core Time (ms) : 0.28 TIDL Subgraphs Processing Time (ms) : 0.24 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 12970373 bytes MEM: Free's : 26 free's of 12970373 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1446] | 0 | - | 0.39 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638b43a70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.47 Core Time (ms) : 0.47 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1147] | 1 | True | 0.96 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ad5100 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.41s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.46s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12236s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12244s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003096300138328235 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 33.24 Core Time (ms) : 29.36 TIDL Subgraphs Processing Time (ms) : 29.26 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59764861 bytes MEM: Free's : 26 free's of 59764861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1665] | 0 | - | 0.35 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd98ad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.08 Core Time (ms) : 1.08 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_925] | 0 | - | 0.74 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628813003960 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.76 Core Time (ms) : 8.76 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_113] | 1 | True | 0.30 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745fa0b010 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1508s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031006061166210093 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 3.66 Core Time (ms) : 3.04 TIDL Subgraphs Processing Time (ms) : 2.98 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18793213 bytes MEM: Free's : 26 free's of 18793213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_132] | 1 | True | 4.55 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926a8b20 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.93s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1439s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0060195041117528025 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 389.13 Core Time (ms) : 331.14 TIDL Subgraphs Processing Time (ms) : 328.57 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 778891509 bytes MEM: Free's : 26 free's of 778891509 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1894] | 0 | - | 0.84 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868808d10 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 104.54 Core Time (ms) : 104.54 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1893] | 0 | - | 0.63 | |
|
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x614b0d2fff70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 13.51 Core Time (ms) : 13.51 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1964] | 0 | - | 1.43 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d2039f30 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 33.69 Core Time (ms) : 33.69 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_227] | 0 | - | 0.57 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a399cc60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.09 Core Time (ms) : 1.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1807] | 0 | - | 1.92 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc383550 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 8.37 Core Time (ms) : 8.37 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_610] | 0 | - | 0.32 | |
|
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5bbbb1fe7180 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_337] | 0 | - | 0.85 | |
|
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x564638c2df70 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.65 Core Time (ms) : 2.65 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1387] | 0 | - | 1.21 | |
|
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e0516dd9d60 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 7.09 Core Time (ms) : 7.09 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_523] | 0 | - | 0.29 | |
|
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d6fbcd99130 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1062] | 0 | - | 0.26 | |
|
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x574ecabb3820 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.15 Core Time (ms) : 0.15 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1929] | 0 | - | 0.43 | |
|
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x63745fa0bb50 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.20 Core Time (ms) : 1.20 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1099] | 1 | True | 0.84 | |
|
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5921467e2fd0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.70s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0012946247845935534 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 34.31 Core Time (ms) : 30.71 TIDL Subgraphs Processing Time (ms) : 30.65 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 76366549 bytes MEM: Free's : 26 free's of 76366549 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1633] | 1 | True | 0.70 | |
|
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6056a399f280 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.79s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1426s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.00031019448319586604 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 21.30 Core Time (ms) : 18.55 TIDL Subgraphs Processing Time (ms) : 18.48 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 59979853 bytes MEM: Free's : 26 free's of 59979853 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1114] | 0 | - | 0.33 | |
|
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x628812f1b9e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.50 Core Time (ms) : 0.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_275] | 0 | - | 0.31 | |
|
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c8321ad6250 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1802] | 0 | - | 0.55 | |
|
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x584868808de0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.25 Core Time (ms) : 1.25 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_502] | 0 | - | 0.24 | |
|
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x59d8e7bbc8b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.07 Core Time (ms) : 0.07 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_354] | 1 | True | 0.39 | |
|
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5e88d203a830 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.99s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1485s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.0003101100567545889 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 11.70 Core Time (ms) : 9.92 TIDL Subgraphs Processing Time (ms) : 9.83 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36356861 bytes MEM: Free's : 26 free's of 36356861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1430] | 0 | - | 0.30 | |
|
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5d31bc29a6e0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.42 Core Time (ms) : 2.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_221] | 0 | - | 2.98 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa529ad0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 91.93 Core Time (ms) : 91.93 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_99] | 1 | True | 0.14 | |
|
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x651d69fc3190 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.122s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1892s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.59 Core Time (ms) : 0.49 TIDL Subgraphs Processing Time (ms) : 0.43 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_646] | 0 | - | 0.06 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba10442a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.42 Core Time (ms) : 0.42 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1711] | 0 | - | 0.14 | |
|
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x6354926a92b0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 0.38 Core Time (ms) : 0.38 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1901] | 1 | True | 0.10 | |
|
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x613ba0f5af60 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.102s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1424s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 7.758413258513111e-05 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 0.62 Core Time (ms) : 0.55 TIDL Subgraphs Processing Time (ms) : 0.49 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 13157117 bytes MEM: Free's : 26 free's of 13157117 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1379] | 0 | - | 0.37 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad14fd0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 12.46 Core Time (ms) : 12.46 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1931] | 1 | True | 0.16 | |
|
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5b000ad15af0 Final number of subgraphs created are : 1, - Offloaded Nodes - 1, Total Nodes - 1 The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO MAX_NMSE: 0.000310000031183446 PERFORMANCE: Num TIDL Subgraphs : 1 Total Time (ms) : 10.80 Core Time (ms) : 8.03 TIDL Subgraphs Processing Time (ms) : 7.91 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33726621 bytes MEM: Free's : 26 free's of 33726621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!! | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1745] | 0 | - | 0.06 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529ac9ed0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.03 Core Time (ms) : 1.03 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_223] | 0 | - | 0.11 | |
|
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x567529acb1a0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 2.50 Core Time (ms) : 2.50 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_359] | 0 | - | 0.14 | |
|
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5ad1aa52aff0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 1.60 Core Time (ms) : 1.60 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1136] | 0 | - | 0.16 | |
|
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x5c373b20f860 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 89.29 Core Time (ms) : 89.29 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||
| Passed | test_tidl_unit.py::test_tidl_unit_operator[Resize_1722] | 0 | - | 0.10 | |
|
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 [gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3 ------------------------------Captured stdout call------------------------------ libtidl_onnxrt_EP loaded 0x60e4584aa6c0 Final number of subgraphs created are : 0, - Offloaded Nodes - 0, Total Nodes - 1 MAX_NMSE: 0 PERFORMANCE: Num TIDL Subgraphs : 0 Total Time (ms) : 42.33 Core Time (ms) : 42.33 TIDL Subgraphs Processing Time (ms) : 0.00 DDR Read Bandwidth (MB/s) : 0.00 DDR Write Bandwidth (MB/s) : 0.00 | |||||